參數(shù)資料
型號(hào)： HT48CA3
廠商： Holtek Semiconductor Inc.
英文描述： 8-Bit Remote Type MCU
中文描述： 8位遙控型單片機(jī)
文件頁(yè)數(shù)： 10/36頁(yè)
文件大?。?/td> 271K
代理商： HT48CA3
HT48CA3
Rev. 1.40
10
July 16, 2003
in port A can be independently selected to wake up the
device by mask option. Awakening from an I/O port
stimulus, the program will resume execution of the next
instruction. If it awakens from an interrupt, two se-
quence may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
will resume execution at the next instruction. If the inter-
rupt is enabled and the stack is not full, the regular inter-
rupt response takes place. If an interrupt request flag is
set to 1 before entering the HALT mode, the wake-up
function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 t
SYS
(system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
Therearethreewaysinwhicharesetcanoccur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set thatresetsonlythePCandSP,leavingtheothercir-
cuits in their original state. Some registers remain un-
changed during other reset conditions. Most registers
are reset to the initial condition when the reset condi-
tions are met. By examining the PD and TO flags, the
programcandistinguishbetweendifferent chipresets .
TO
PD
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
The functional unit chip reset status are shown below.
PC
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter
Off
Input/output Ports
Input mode
SP
Points to the top of the stack
!
, #
9
!
) # " , ,
!
Reset timing chart
Reset circuit
+
,
!
+
= $ (
'
!
&
!
,
!
9 < # ! ,
# " "
!
Reset configuration
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HT48E06 8-Bit I/O Type MCU (With EEPROM)
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