參數(shù)資料
型號: HT48C10
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit Microcontroller Series
中文描述: 8位微控制器系列
文件頁數(shù): 18/59頁
文件大?。?/td> 2625K
代理商: HT48C10
L abels
Bits
F unction
C
0
C is set if the operation results in a carry during an addition operation or if a
borrow does not take place during a subtraction operation; otherwise C is
cleared. Also it is affected by a rotate through carry instruction.
AC is set if the operation results in a carry out of the low nibbles in addition or
no borrow from the high nibble into the low nibble in subtraction; otherwise AC
is cleared.
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD is cleared by either a system power-up or executing the CLR WDT
instruction. PD is set by executing the HALT instruction.
TO is cleared by a system power-up or executing the CLR WDT or HALT
instruction. TO is set by a WDT time-out.
Undefined, read as 0
Undefined, read as 0
AC
1
Z
2
OV
3
PD
4
TO
5
6
7
Status register
On entering the interrupt sequence or execut-
ing the subroutine call, the status register will
not be automatically pushed onto the stack . If
the contents of the status is important and the
subroutine can corrupt the status register, the
programmer should take precautions to save it
properly.
Interrupt
The four microcontrollers all provide an exter-
nal interrupt and internal timer/event counter
interrupts. T he interrupt control register
(INTC;0BH) contains interrupt control bits for
setting the enable/disable mode and the interrupt
request flags.
Once an interrupt subroutine is serviced, the
remaining interrupts will all be blocked (by
clearing the E MI bit). This scheme may prevent
any further interrupt nesting. Other interrupt
requests may happen during this interval but
only the interrupt request flag will be recorded.
If a certain interrupt requires servicing within
the service routine, the programmer may set the
EMI bit and the corresponding bit of INTC so as
to allow interrupt nesting. If the stack is full, the
interrupt request will not be acknowledged, even
if the related interrupt is enabled, until the SP
is decremented. If immediate servicing is de-
sired, the stack should be prevented from be-
coming full.
All these interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer
occurs by pushing the PC onto the stack and
then by branching it to subroutines at the speci-
fied location(s) in the ROM. Only the contents of
the PC can be pushed onto the stack. If the
contents of the register and of the status regis-
ter (STATUS) are altered by the interrupt serv-
ice program which corrupts the desired control
sequence, the programmer should save these
contents first.
The external interrupt is triggered by a high to
low transition of the INT, and the related inter-
rupt request flag (E IF; bit 4 of INTC) is then set.
When the interrupt is enabled, the stack is not
full, and the external interrupt is active, a sub-
routine call to location 04H will occur. The inter-
rupt request flag (E IF) and E MI bits will also be
cleared to disable other interrupts.
Of the four microcontrollers, the internal
timer/event counter interrupt of the HT48C10/
HT48C30 is initialized by setting the timer/
HT48CXX/HT48RXX
18
25th May ’99
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