參數(shù)資料
型號: HSP50306
廠商: Intersil Corporation
英文描述: Digital QPSK Demodulator(數(shù)字QPSK解調(diào)器)
中文描述: 數(shù)字化QPSK解調(diào)器(數(shù)字調(diào)制解調(diào)器)
文件頁數(shù): 7/8頁
文件大小: 37K
代理商: HSP50306
8-278
AC Test Load Circuit
AC Electrical Specifications
27MHz Clock Rate, V
CC
= 5.0V
±
5%, T
A
= 0
o
to 70
o
C (Note 8)
PARAMETER
SYMBOL
NOTES
MIN
MAX
UNITS
CLK Period
t
CP
36
-
ns
CLK High
t
CH
12
-
ns
CLK Low
t
CL
12
-
ns
Setup RESET to CLK
t
RS
15
-
ns
Hold Time RESET to CLK
t
RH
1
-
ns
Setup Time DIN0-5 to ADCLK
t
DS
9
15
-
ns
Hold Time DIN0-5 to ADCLK
t
DH
9
2
-
ns
CLK to DATAOUT, LOCK, AGCOUT
t
PD
-
25
ns
Output Rise, Fall Time
t
RF
10
-
8
ns
Output Rise, Fall Time (CMOS Outputs)
t
TC
10
-
12
ns
NOTES:
8. AC Testing is performed as follows: Input levels 0.0V to 3.0V. Timing reference levels = 1.5V. Output load circuit with C
L
= 40pF. Output
transition measured at V
OH
_1.5V and V
OL
_1.5V.
9. The set up and hold times for DIN (5:0) are with respect to the rising edge of ADCLKOUT. These parameters are guaranteed by design
and characterization but not tested. An A/D converter with a clock to data out specification of 55ns and a data hold from clock specification
of 2ns will meet these requirements at an oscillator clock frequency of 26.97MHz. Intersil recommends the CA3304 or CA3306 A/D con-
verters for use with the HSP50306.
10. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design
changes.
SWITCH S1 OPEN FOR I
CCSB
AND I
CCOP
EQUIVALENT CIRCUIT
C
L
(NOTE)
I
OH
2.5V
I
OL
DUT
S
1
±
NOTE: Test head capacitance
HSP50306
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