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參數(shù)資料
| 型號： | HSP9501JC-32 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Programmable Data Buffer |
| 中文描述： | 10-BIT, DSP-PIPELINE REGISTER, PQCC44 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 49K |
| 代理商： | HSP9501JC-32 |
191
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright Intersil Corporation 1999
HSP9501
Programmable Data Buffer
The HSP9501 is a 10-Bit wide programmable data buffer
designed for use in high speed digital systems. Two different
modes of operation can be selected through the use of the
MODSEL input. In the delay mode, a programmable data
pipeline is created which can provide 2 to 1281 clock cycles
of delay between the input and output data. In the data
recirculate mode, the output data path is internally routed
back to the input to provide a programmable circular buffer.
The length of the buffer or amount of delay is programmed
through the use of the 11-bit Length Control Input Port (LC0-
10) and the Length Control Enable (LCEN). An 11-bit value
is applied to the LC0-10 inputs, LCEN is asserted, and the
next selected clock edge loads the new count value into the
Length Control Register. The delay path of the HSP9501
consists of two registers with a programmable delay RAM
between them, therefore, the value programmed into the
Length Control Register is the desired length - 2. The range
of values which can be programmed into the Length Control
Register are from 0 to 1279, which in turn results in an
overall range of programmable delays from 2 to 1281.
Clock select logic is provided to allow the use of a positive or
negative edge system clock as the CLK input to the
HSP9501. The active edge of the CLK input is controlled
through the use of the CLKSEL input. All synchronous timing
(i.e., data setup, hold, and output delays) are relative to the
clock edge selected by CLKSEL. An additional clock enable
input (CLKEN) provides a means of disabling the internal
clock and holding the existing contents temporarily. All
outputs of the HSP9501 are three-state outputs to allow
direct interfacing to system or multi-use busses.
The HSP9501 is recommended for digital video processing
or any applications which require a programmable delay or
circular data buffer.
Features
DC to 32MHz Operating Frequency
Programmable Buffer Length from 2 to 1281 Words
Supports Data Words to 10-Bits
Clock Select Logic for Positive or Negative Edge
System Clocks
Data Recirculate or Delay Modes of Operation
Expandable Data Word Width or Buffer Length
Three-State Outputs
TTL Compatible Inputs/Outputs
Low Power CMOS
Applications
Sample Rate Conversion
Data Time Compression/Expansion
Software Controlled Data Alignment
Programmable Serial Data Shifting
Audio/Speech Data Processing Video/Image Processing
Video/Image Processing
1-H Delay Line of 910 NTSC, 1135 PAL or 1280 Samples:
- High Resolution Monitor Delay Line
- Comb Filter Designs
- Progressive Scanning Display
- TV Standards Conversion
- Image Processing
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
HSP9501JC-25
0 to 70
44 Ld PLCC
N44.65
HSP9501JC-32
0 to 70
44 Ld PLCC
N44.65
HSP9501JC-2596
0 to 70
44 Ld PLCC
Tape and Reel
N44.65
Data Sheet
January 1999
File Number
2786.4
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