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參數(shù)資料
| 型號： | HSP50306 |
| 廠商： | Intersil Corporation |
| 英文描述： | Digital QPSK Demodulator(數(shù)字QPSK解調(diào)器) |
| 中文描述： | 數(shù)字化QPSK解調(diào)器（數(shù)字調(diào)制解調(diào)器） |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 37K |
| 代理商： | HSP50306 |
8-273
HSP50306
Pinout
16 LEAD SOIC
TOP VIEW
Pin Description
NAME
SOIC PIN
TYPE
DESCRIPTION
V
CC
16
-
+5V Power Supply
GND
8
-
Ground
CLKIN
7
I
Clock input. This is the processing clock for the part. All timing is derived from this clock.
DIN (5:0)
I
I.F. input samples from the A/D converter. These bits interpreted as offset binary format. DIN5 is the
MSB. If fewer than 6 bits are used, the bits from the A/D should be connected to the MSBs of the
input and the unused LSBs grounded.
ADCLK
15
O
This output clock is the clock for the A/D converter.
AGCOUT
1
O
This output indicates whether the magnitude of the input samples are above or below the expected
level. This output is provided as an error detector for an external AGC loop. The output is low when
the input is greater than nominal, and high when the input is lower than nominal.
DATAOUT
3
O
This is the recovered data.
CLKOUT
2
O
This is the recovered clock.
LOCK
4
O
This signal indicates that the carrier tracking loop is locked and data on the DOUT pin should be valid.
RESET
5
I
This input is provided to for initialization and test. Active low.
TEST
6
I
This input is provided for test. Pull high for normal operation.
AGCOUT
CLKOUT
DATAOUT
TEST
CLKIN
GND
V
CC
DIN0
DIN1
DIN2
DIN3
DIN5
ADCLK
DIN4
RESET
LOCK
14
15
16
9
13
12
11
10
2
3
4
5
7
6
8
1
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50306 WAF | 制造商:Intersil Corporation 功能描述: |
| HSP50306_04 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator |
| HSP50306SC-25 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50306SC-2596 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator |
| HSP50306SC-27 | 制造商:Rochester Electronics LLC 功能描述:QPSK DEMODULATOR 16 LEAD SOIC - Bulk |
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