參數(shù)資料
| 型號： | HSP43168JC-33Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 23/25頁 |
| 文件大小： | 0K |
| 描述： | IC FIR FILTER DUAL 84-PLCC |
| 標準包裝： | 15 |
| 濾波器類型： | FIR |
| 濾波器數(shù)： | 2 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應商設備封裝： | 84-PLCC（29.21x29.21） |
| 包裝： | 管件 |
7
FN2808.12
July 27, 2009
The 4 LSBs of the control word loaded at address 000H are
used to select the decimation factor. The Decimation Factor
is programmed to one less than the number of delays
between filter taps as shown in Equation 1.
For example, if the 4 LSBs are programmed with a value of
0010, the Forward and Reverse Shifting Decimation Registers
are each configured with a delay of 3. Bit 4 is used to select
whether the FIR cells operate as two independent filters or
one extended length filter. Dual filter mode assumes Filter A
and Filter B are separate independent filters. In the single filter
mode, the data is routed through the forward paths of Filters A
and B before entering the reverse paths of Filters A and B
(see Figure 1). Coefficient symmetry is selected by bit 5. Bits 6
and 7 are programmed to configure the FIR cells for odd or
even filter lengths (number of taps). Bit 8 selects the FIR B
input source when the FIR cells are configured for
independent operation. Bit 9 must be programmed to 0.
Note: When the filter is programmed for even-taps, the
TXFR signal is delayed by only three CLKS (see Figure 1).
For odd-taps, the TXFR signal is delayed by four CLKS.
The 4 LSBs of the control word loaded at address 001H are
used to configure the format of the FIR cell's data and
coefficients. Bit 4 is programmed to enable or disable the
reversal of data sample order prior to entering the Reverse
Path Decimation Registers. Data reversal is required for
symmetric filter coefficient sets of both even or odd numbers
of filter taps. Asymmetric filters and some decimated
symmetric filters require the data reversal to be off. Bits 5 to
9 are used to support programmable rounding on the output.
FIR Filter Cells
Each FIR filter cell is based on an array of four 11x10-bit two's
complement multipliers. One input of the multipliers comes
from the ALU’s which combine data shifting through the
Forward and Reverse Decimation Registers. The second
multiplier input comes from the user programmable coefficient
bank. The multiplier outputs are fed to an accumulator whose
result is passed to the output section where it is multiplexed or
added with the result from the other FIR cell.
Decimation Registers
The Forward and Reverse Decimation Shift Registers can
be configured for decimation factors from 1 to 16 (see
Table 1, bits 0-3). Note: Setting the decimation factor
only affects the Delay Registers between filter taps, not
the filter control multiplexers. Example 4 and Example 5
in “Application Examples” on page 10 discuss how to
configure the part for actual decimation applications.
The Reverse Shifting Registers with the data reversal logic
are used to take advantage of symmetry in linear phase filters
by aligning data at the ALUs for pre-addition prior to
multiplication by the common coefficient. When the FIR cells
are configured in single filter mode, the Decimation Registers
in FIR cell A and FIR cell B are cascaded. This extended filter
tap delay path allows computation of a filter which is twice the
size of that capable using a single cell. The Decimation
Registers also provide data storage for polyphase or 2-D
filtering applications (See “Application Examples” on
The Data Feedback Circuitry in each FIR cell is responsible
for transferring data from the Forward to the Reverse
Shifting Decimation Registers. This circuitry feeds blocks of
samples into the reverse shifting decimation path in either
reversed or non-reversed sample order. The MUX/DEMUX
structure at the input to the Feedback Circuitry routes data
to the LIFOs or the delay stage depending on the selected
TABLE 1. CONFIGURATION/CONTROL WORD 0 BIT
DEFINITIONS
CONTROL ADDRESS 000H
BITS
FUNCTION
DESCRIPTION
3-0
Decimation Factor (N) R = N + 1
0000 = No Decimation.
1111 = Decimation by 16.
4
Mode Select
0 = Single Filter Mode.
1 = Dual Filter Mode.
(also 20-Bit Coefficient Filter)
5
Odd/Even Filter
Coefficient Symmetry
0 = Even Symmetric Coefficients.
1 = Odd Symmetric Coefficients.
6
FIR A Odd/Even
Number of Taps
0 = Odd Number of Taps in Filter.
1 = Even Number of Taps in Filter.
7
FIR B Odd/Even
Number of Taps
(Defined Same as FIR A Above).
8
FIR B Input Source
0 = Input from INA0-9.
1 = Input from INB0-9.
9
Not Used
Set to 0 for Proper Operation.
TABLE 2. CONFIGURATION/CONTROL WORD 1 BIT
DEFINITIONS
CONTROL ADDRESS 001H
BITS
FUNCTION
DESCRIPTION
0
FIR A Input Format
0 = Unsigned.
1 = Two's Complement.
1
FIR A Coefficient Format
(Defined same as FIR A input).
2
FIR B Input Format
(Defined same as FIR A input).
3
FIR B Coefficient
(Defined same as FIR A input).
4
Data Reversal Enable
0 = Enabled.
1 = Disabled.
8-5
Round Position
0000 = 2-10.
1011 = 21.
(See Figure 4)
9
Round Enable
0 = Enabled.
1 = Disabled.
NOTES:
1. Address locations 002H to 011H are reserved, and writing to
these locations will have unpredictable effects on part
configuration.
DF
CLK delays between taps
() 1
–
=
(EQ. 1)
HSP43168
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