參數(shù)資料
型號(hào)： HSP43168JC-33Z
廠商： Intersil
文件頁(yè)數(shù)： 10/25頁(yè)
文件大?。?/td> 0K
描述： IC FIR FILTER DUAL 84-PLCC
標(biāo)準(zhǔn)包裝： 15
濾波器類型： FIR
濾波器數(shù)： 2
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC（29.21x29.21）
包裝： 管件
18
FN2808.12
July 27, 2009
To operate in this mode, the Dual is configured by writing
112H to Address 000H via the microprocessor interface,
CIN0-9, A0-8, and WR. Data reversal must be enabled (see
Table 2). The 12 unique coefficients for this example are
stored as three sets of coefficients for either FIR cell. For FIR
A, the coefficients are loaded into the Coefficient Bank by
writing [C2, C5, C8, (C11)/ 2], CSEL = 0; [C1, C4, C7, C10],
CSEL = 1; [C0, C3, C6, and C9], CSEL = 2; to address
100H, 101H, 102H, 103H, 108H, 109H, 10aH, 10bH, 110H,
111H, 112H, and 113H, respectively.
Example 6. Dual Decimation Example
The purpose of this example is to give an overview of one of
the more complex applications of the HSP43168. The input
is two data streams (A) and (B) samples. Figure 23 shows
the upper level block diagram of the system being
implemented. The decimation rate was set to N. N-1 is
loaded into the decimation factor in Control Word 000H.
To demonstrate the muxed decimation, lets suppose that the
application requires filter A to be configured as an
even-decimate-by-3 filter and filter B to be configured as a
odd-decimate-by-3 filter. The output data is made of the two
decimated data streams multiplexed together and has a data
rate equal to 2x the input sampling rate divided by the
decimation factor. Figure 24 shows the data/coefficient
alignment for FIR A and FIR B.
To operate in this mode, Control Word 000H must be written
with a 0x152. Data reversal must be enabled by setting bit 4
of Control Word 001H = 0. The filter set selected by
CSEL0-4 = 0 should be loaded by writing C2, C5, C8, C11,
D2, D5, D8, and (D11)/ 2 into 100H, 101H, 102H, 103H,
104H, 105H, 106H, and 107H. The filter set selected by
CSEL0-4 = 1 should be loaded by writing C1, C4, C7, C10,
D1, D4, D7, and D10 into 108H, 109H, 10aH, 10bH, 10cH,
10dH, 10eH, and 10fH. The filter set selected by
CSEL0-4 = 2 should be loaded by writing C0, C3, C6, C9,
D0, D3, D6, and D9 into 110H, 111H, 112H, 113H, 114H,
115H, 116H, and 117H.
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
C11
FIGURE 21. DATA/COEFFICIENT ALIGNMENT FOR 23-TAP
DECIMATE BY 3 SYMMETRIC FILTER
h(n)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876
5 43210
x(n)
23-TAPS
01
2
3
5
20
21
22
0
01
2
0
CLK
INA0-9
CSEL0-4
ACCEN
TXFR
12
3
4
5
4
22
23
21
1
2
01
2
Tied low.
FIGURE 22. CONTROL SIGNAL TIMING FOR 23-TAP
SYMMETRIC FILTER
FWRD
RVRS
SHIFTEN
A3, A2, A1, A0
B3, B2, B1, B0
HSP43168
INB0-9
INA0-9
FS
DECIMATE BY N
2FS/(N+1)
OUT9-27
AOUT1
BOUT0
AOUT0
BOUT1
FIGURE 23. MULTIPLEXED DECIMATION BLOCK DIAGRAM
HSP43168
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