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參數(shù)資料
| 型號： | HSP43124 |
| 廠商： | Intersil Corporation |
| 英文描述： | RESISTOR 3.3 OHM 20W TO220 |
| 中文描述： | 串行I / O過濾器 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大小： | 144K |
| 代理商： | HSP43124 |
14
FCLK/SCLK Uncertainty Region
Figure 13 shows a clocking relationship for the HSP43124
Serial I/O filter that could result in an uncertainty at the
output. For simplicity, the frequency of FCLK and SCLK are
assumed to be equal to each other, and CLKOUT is
assumed to be equal to FLCK. When the rising edge of
FCLK lags behind the rising edge of SCLK by a small
amount of time (T
SCFC
), then the FCLK edge on which
samples are read into the filter compute engine is
determined by a race condition. In order to insure proper
function for the HSP43124, T
SCFC
must be greater than
3.8ns.
If exact timing (a particular clock edge for a specific data bit)
then make SCLK and FCLK synchronous. If FCLK and
SCLK are asynchronous, there will be jitter (a specific data
bit will be output as 1 of 2 possible clock edges depending
on the FCLK to SCLK phasing). For multiple part
applications, use synchronous clocks or use separate syncs
on what receives each data, as the outputs may vary by a
clock cycle.
Asynchronous FCLK and SCLK
If FCLK and SCLK are asynchronous clocks, then the output
sample rate (tracked by SYNCOUT) of the HSP43124 might
jitter in a real time system. This jitter will be demonstrated
using an SCLK with a period that is 3/2 times the period of
FCLK (i.e., F
FCLK
/F
SCLK
= 3/2), as shown in Figure 14A
and Figure 14B. If the LSB occurs when there are two FCLK
edges in one SCLK period (see Figure 14A), then a null data
bit will occur in the DOUT data stream. If the LSB occurs
when there is one FCLK edge in one SCLK period for the
LSB (see Figure 14B), then no null data bit will occur. Given
the 3/2 period relationship between FCLK and SCLK, the
user can see that the SYNCOUT jitters by one clock. For
example, if the output data is represent by 16 bits, then the
number of CLKOUT rising edges between SYNCOUT pulses
should jitter between 15 and 16.
The SYNCOUT jitter demonstrated by the 3/2 frequency
example can be generalized to other asynchronous
F
FCLK
/F
SCLK
ratios. Setting the frequencies for FCLK and
SCLK at integer multiples of one another eliminates timing
jitter in the output sample rate.
SCLK
SYNCIN
DIN
FCLK
SYNCOUT
DOUT
T
SCFC
MSB
MSB
LSB
LSB
MSB
MSB
FIGURE 13. FCLK/SCLK UNCERTAINTY REGION
FIGURE 14A. NUMBER OF CLKOUT = NUMBER OF BITS + 1
FOR THE TIME PERIOD BETWEEN SYNCOUTS
WHERE F
FCLK
/F
SCLK
= 3/2
FIGURE 14B. NUMBER OF CLKOUT = NUMBER OF BITS FOR
THE TIME PERIOD BETWEEN SYNCOUTS
WHERE F
FCLK
/F
SCLK
= 3/2
SCLK
SYNCIN
DIN
CLKOUT
SYNCOUT
DOUT
MSB
MSB
LSB
NULL
MSB
LSB
MSB
1
2
1
2
SCLK
SYNCIN
DIN
CLKOUT
SYNCOUT
DOUT
MSB
MSB
MSB
MSB
LSB
LSB
1
2
1
2
HSP43124
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP43168GC-45 | Dual FIR Filter |
| HSP43168VC-33 | Dual FIR Filter |
| HSP43168VC-40 | Dual FIR Filter |
| HSP43168VC-45 | Dual FIR Filter |
| HSP43168 | Dual FIR Filter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP43124_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Serial I/O Filter |
| HSP43124PC-33 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Serial I/O Filter |
| HSP43124PC-45 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HSP43124SC-33 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP43124SC-45 | 功能描述:有源濾波器 24 BIT SERIAL I/O FILTER 28 SOIC, 45MHZ, RoHS:否 制造商:Maxim Integrated 通道數(shù)量:1 截止頻率:150 KHz 電源電壓-最大:11 V 電源電壓-最小:4.74 V 最大工作溫度:+ 85 C 安裝風格:Through Hole 封裝 / 箱體:PDIP N 封裝:Tube |
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