參數(shù)資料
型號(hào)： HS9-RTX2010RH
廠商： Intersil Corporation
英文描述： Radiation Hardened Real Time Express⑩ Microcontroller
中文描述： 輻射加固實(shí)時(shí)快遞⑩微控制器
文件頁數(shù)： 13/36頁
文件大小： 406K
代理商： HS9-RTX2010RH
13
: The Interrupt Mask Register has a bit assigned for
each maskable interrupt which can occur. When a bit is set,
the interrupt corresponding to that bit will be masked. Only
the Non-Maskable Interrupt (NMI) cannot be masked. See
Figure 14 for bit assignments for this register.
Stack Controller Registers
: The Stack Pointer Register holds the stack pointer
value for each stack. Bits 0-7 represent the next available
stack memory location for the Parameter Stack, while bits 8-
15 represent the next available stack memory location for the
Return Stack. These stack pointer values must be accessed
together, as
. See Figure 15.
SPR
: The Stack Overflow Limit Register is a write-only
register which holds the overflow limit values (0 to 255) for
the Parameter Stack (bits 0-7) and the Return Stack (bits
8-15). These values must be written together. See Figure 16.
: The Stack Underflow Limit Register holds the
underflow limit values for the Parameter Stack and the
Return Stack. In addition, this register is utilized to define the
use of substacks for both stacks. These values must be
accessed together. See Figure 17.
0
1
2
3
4
5
6
7
8
9
1514
12
13
10
READ-ONLY; FATAL
STACK ERROR FLAG
READ-ONLY; PARAMETER
STACK UNDERFLOW FLAG
READ-ONLY; PARAMETER
STACK OVERFLOW FLAG
READ-ONLY; RETURN
STACK UNDERFLOW FLAG
READ-ONLY; RETURN
STACK OVERFLOW FLAG
SVR
IBC
PARAMETER STACK
FATAL ERROR
RETURN STACK FATAL ERROR
DPRSEL: SELECTS
PAGE REGISTER FOR
DATA MEMORY ACCESS
= 1: SELECT
= 0: SELECT
SUR
CPR
DPR
ROUND: MULTIPLIER
CONTROL BIT; SELECTS
ROUNDING OF 16 x 16
BIT MULTIPLICATION
= 1: ROUNDED 16-BIT
PRODUCT
= 0: UNROUNDED
32-BIT PRODUCT
INPUT SIGNALS: TCLK
OR EI5 - EI3 (TABLE 6)
SELECT TIMER/COUNTER
CYCEXT: ALLOWS
EXTENDED CYCLE LENGTH
FOR USER MEMORY
INSTRUCTION CYCLES; SEE
CLOCK AND WAIT
TIMING DIAGRAMS
M
M
M
M
M
M
I
I
B
11
FIGURE 13.
BIT ASSIGNMENTS
IBC
IMR
RSV, RETURN STACK
OVERFLOW
EI2
TCI 0
TCI 1
TCI 2
EI3
EI4
EI5
SWI
RESERVED (NOTE)
PSV, PARAMETER STACK
OVERFLOW
RSU, RETURN STACK
UNDERFLOW
PSU, PARAMETER STACK
UNDERFLOW
EI1
(EXTERNAL INPUT PIN)
IMR
8
1514
12
13
9
10
11
0
1
2
3
4
5
6
7
RESERVED (NOTE)
NOTE: Always read as ‘‘0’’. Should be set = 0 during Write operations.
FIGURE 14.
BIT ASSIGNMENTS
IMR
SPR
SVR
SUR
8
9
PSP, PARAMETER STACK
POINTER
RSP, RETURN STACK
POINTER
0
1
2
3
4
5
6
7
SPR
10
11
15141312
FIGURE 15.
BIT ASSIGNMENTS
SPR
PVL: PARAMETER
STACK OVERFLOW LIMIT.
NUMBER OF WORDS FROM
TOP OF CURRENT SUBSTACK
RVL: RETURN STACK
OVERFLOW LIMIT.
NUMBER OF WORDS FROM
TOP OF CURRENT SUBSTACK
BIT ASSIGNMENTS
SVR
8
0
1
2
3
4
5
6
7
9
14
15
1312 1110
FIGURE 16.
SVR
HS-RTX2010RH
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