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參數(shù)資料
| 型號(hào)： | HS9-RTX2010RH-Q |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | Radiation Hardened Real Time Express⑩ Microcontroller |
| 中文描述： | 16-BIT, 8 MHz, MICROCONTROLLER, CQFP84 |
| 封裝： | CERAMIC, QFP-84 |
| 文件頁(yè)數(shù)： | 10/36頁(yè) |
| 文件大小： | 406K |
| 代理商： | HS9-RTX2010RH-Q |
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10
HS-RTX2010RH Operation
Control of all data paths and the Program Counter Register,
(
), is provided by the Instruction Decoder. This hardware
determines what function is to be performed by looking at
the contents of the Instruction Register, (
subsequently determines the sequence of operations
through data path control.
), and
Instructions which do not perform memory accesses execute
in a single clock cycle while the next instruction is being
fetched.
As shown in Figure 10, the instruction is latched into
the beginning of a clock cycle. The instruction is then decoded
by the processor. All necessary internal operations are
performed simultaneously with fetching the next instruction.
at
Instructions which access memory require two clock cycles
to be executed. During the first cycle of a memory access
instruction, the instruction is decoded, the address of the
memory location to be accessed is placed on the Memory
Address Bus (MA19-MA01), and the memory data
(MD15-MD00), is read or written. During the second cycle,
ALU operations are performed, the address of the next
instruction to be executed is placed on the Memory Address
Bus, and the next instruction is fetched, as indicated in the
bottom half of Figure 10.
BYTE
SWAP
HS-RTX2010RH
OFF-CHIP
USER
INTERFACES
TIMER/COUNTERS
TC0
TC1
TC2
TP0
TP1
TP2
ALU
Y
T
PC
I
TOP
CR
MD
SR
CONTROL
SPR
SVR
STACK
IMR
IVR
IBC
CONTROL
INTERRUPT
(
CPAGE
IPR
MEMORY
CLOCK AND
CONTROL
RESET
INTERFACE
MEMORY BUS
INTERFACE
ASIC BUS
DPR
UPR
CPR
UBR
SUR
E
E
I
N
I
I
W
P
T
R
U
L
N
B
M
M
M
M
M
G
G
G
G
G
G
-
1
+1
INSTRUCTION
DECODER
IR
LEADING ZERO
DETECTOR
16 x 16
MAC
BARREL
SHIFTER
MXR
MHR
MLR
256 x 21
RETURN
STACK
MEMORY
256 x 16
PARAMETER
STACK
MEMORY
NEXT
NOTE:
contains the 5 most significant bits (20-16) of the top element of the Return Stack.
FIGURE 9. HS-RTX2010RH FUNCTIONAL BLOCK DIAGRAM
IPR
PC
IR
IR
HS-RTX2010RH
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| HS1-1825ARH-8 | ER 2C 2#8 SKT RECP WALL |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HS9S-117RH/PROTO | 制造商:Intersil Corporation 功能描述: |
| HS9S-117RH-8 | 制造商:Intersil Corporation 功能描述:REG STD LIN ADJ POS 1.2V TO 37V 1.25A 3PIN SOT-23 - Trays |
| HS9S-117RH-8S2740 | 制造商:Intersil Corporation 功能描述:RADIATION HARDENED LINEAR VOLTAGE REGULATOR, CLASS Q, 36MDC, - Trays |
| HS9S-117RHPROTO | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Radiation Hardened Adjustable Positive Voltage Regulator |
| HS9S-117RH-Q | 制造商:Intersil Corporation 功能描述:REG STD LIN ADJ POS 1.2V TO 37V 1.25A 3PIN SOT-23 - Trays |
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