參數(shù)資料
型號(hào)： HS9-RTX2010RH-8
廠(chǎng)商： INTERSIL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： Radiation Hardened Real Time Express⑩ Microcontroller
中文描述： 16-BIT, 8 MHz, MICROCONTROLLER, CQFP84
封裝： CERAMIC, QFP-84
文件頁(yè)數(shù)： 28/36頁(yè)
文件大?。?/td> 406K
代理商： HS9-RTX2010RH-8
28
Whenever a word of data is read by a Data Memory operation
into the processor, it is first placed in the
the time the instruction that reads that word of data is
completed, however, the data may have been moved,
optionally inverted, or operated on by the ALU, and placed in
the
Register. Whenever a Data Memory operation
writes to memory, the data comes from the
Register. By
NEXT
Register.
The Byte Order Bit is bit 2 of the Configuration Register,
(see Figure 11 in the “RTX Internal Registers
Section). This bit is used to determine whether the default
(Mode 0) or byte swap (Mode 1) method will be used in the
Data Memory accesses.
Word Access is designated when the
Memory Access Opcode, and can take one of two forms,
depending upon the status of
bit 12 = 0 in the
, bit 2.
When
designated. Word access to an even address (A0 = 0) results
in an unaltered transfer of data, as shown in Figure 26. Word
access to/from an odd address (A0 = 1) while in this mode will
effectively cause the Byte Order Bit to be complemented and
will result in the bytes being swapped.
bit 2 = 0, the Mode 0 method of word access is
When the
access is designated. Access to an even address (A0 = 0)
results in a data transfer in which the bytes are swapped.
Word access to an odd address (A0 = 1) while in this mode
will effectively cause the Byte Order Bit to be complemented
with the net result that no byte swap takes place when the
data word is transferred. See Figure 26.
bit 2 = 1, the Mode 1 method of word
Byte Access is designated when the
Memory Access Opcode, and can also take one of two
forms, depending on the value of
bit 12 = 1 in the
Bit 2.
When the
address in Mode 0 causes the upper byte (MD15-MD08) of
memory data to be read into the lower byte position
(MD07-MD00) of
, while the upper byte (MD15-MD08)
is set to 0. A Byte Write operation accessing an even
address will cause the byte to be written from the lower byte
position (MD07-MD00) of
(MD15-MD08) of memory. The data in the lower byte
position (MD07-MD00) in memory will be left unaltered.
Accessing an odd address for either of these operations will
cause the Byte Order Bit to be complemented, with the net
result that no swap will occur. See Figure 27.
bit 2 = 0, a Byte Read from an even
into the upper byte position
When
access is used. Accessing an even address in this mode
means that a Byte Read operation will cause the lower byte
of data to be transferred without a swap operation. A Byte
Write in this mode will also result in an unaltered byte
transfer. Conversely, accessing an odd address for a byte
operation while in Mode 1 will cause the Byte Order Bit to be
complemented. In a Byte Read operation, this will result in
the upper byte (MD15-MD08) of data being swapped into the
bit 2 = 1, the Mode 1 method of memory
lower byte position (MD07-MD00), while the upper byte is
set to 0 (MD15-MD08 set to 0). See Figure 27. A Byte Write
operation accessing an odd address will cause the byte to
be swapped from the lower byte position (MD07-MD00) of
the processor register into the upper byte position
(MD15-MD08) of the Memory location. The data in the lower
byte position (MD07-MD00) in that Memory location will be
left unaffected.
NOTE: These features are for Main Memory data access only, and
have no effect on instruction fetches, long literals, or User Data
Memory.
Subroutine Calls And Returns
The RTX can perform both “short” subroutine calls and
“l(fā)ong” subroutine calls. A short subroutine call is one for
which the subroutine code is located within the same Code
page as the Call instruction, and no processor cycle time is
expended in reloading the
CPR
.
Performing a long subroutine call involves transferring
execution to a different Code page. This requires that the
be loaded with the new Code page as described in
the Memory Access Section, followed immediately by the
Subroutine Call instruction. This adds two additional cycles
to the execution time for the Subroutine Call.
For all instructions except Subroutine Calls or Branch
instructions, bit 5 of the instruction code represents the
Subroutine Return Bit. If this bit is set to 1, a Return is
performed whereby the return address is popped from the
Return Stack, as indicated in Figure 19. The page for the
return address comes from the
Register are written to the
the
are written to the
at the point following the Subroutine Call. The Return Stack
is also popped at this time.
. The contents of the
, and the contents of
so that execution resumes
HS-RTX2010RH Software
The HS-RTX2010RH is designed around the same
architecture as the RTX 2000, and is a hardware
implementation of the Virtual Forth Engine. As such, it does
not require the additional assembly or machine language
software development typical of most real-time
microcontrollers.
The instruction set for the HS-RTX2010RH TForth compiler
combines multiple high level instructions into single machine
instructions without having to rely on either pipelines or
caches. This optimization yields an effective throughput
which is faster than the processor’s clock speed, while
avoiding the unpredictable execution behavior exhibited by
most RISC processors caused by pipeline flushes and cache
misses.
2010 Compilers
Intersil offers a complete ANSI C cross development
environment for the HS-RTX2010RH. The environment
provides a powerful, user-friendly set of software tools
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HS-RTX2010RH
相關(guān)PDF資料
PDF描述
HS-RTX2010RH Radiation Hardened Real Time Express⑩ Microcontroller
HS8-RTX2010RH Radiation Hardened Real Time Express⑩ Microcontroller
HS9-RTX2010RH Radiation Hardened Real Time Express⑩ Microcontroller
HS8-RTX2010RH-Q Radiation Hardened Real Time Express⑩ Microcontroller
HS9-RTX2010RH-Q Radiation Hardened Real Time Express⑩ Microcontroller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HS9-RTX2010RH-Q 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Radiation Hardened Real Time Express⑩ Microcontroller
HS9S-117RH/PROTO 制造商:Intersil Corporation 功能描述:
HS9S-117RH-8 制造商:Intersil Corporation 功能描述:REG STD LIN ADJ POS 1.2V TO 37V 1.25A 3PIN SOT-23 - Trays
HS9S-117RH-8S2740 制造商:Intersil Corporation 功能描述:RADIATION HARDENED LINEAR VOLTAGE REGULATOR, CLASS Q, 36MDC, - Trays
HS9S-117RHPROTO 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Radiation Hardened Adjustable Positive Voltage Regulator
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