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參數(shù)資料
| 型號： | HS8-RTX2010RH-Q |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Radiation Hardened Real Time Express⑩ Microcontroller |
| 中文描述： | 16-BIT, 8 MHz, MICROCONTROLLER, CPGA85 |
| 封裝： | PGA-85 |
| 文件頁數(shù)： | 8/36頁 |
| 文件大小： | 406K |
| 代理商： | HS8-RTX2010RH-Q |
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8
NOTES:
11. Events in an interrupt sequence are as follows:
e
1
. The Interrupt Controller samples the interrupt request inputs on the rising edge of PCLK. If NMI rises between e
1
and the rising edge of
PCLK prior to e
5
, the interrupt vector will be for NMI.
e
2
. If any interrupt requests were sampled, the Interrupt Controller issues an interrupt request to the core on the falling edge of PCLK.
e
3
. The core samples the state of the interrupt requests from the Interrupt Controller on the falling edge of PCLK. If INTSUP is high, maskable
interrupts will not be detected at this time.
e
4
. When the core samples an interrupt request on the falling edge of PCLK, an Interrupt Acknowledge cycle will begin on the next rising edge
of PCLK.
e
5
. Following the detection of an interrupt request by the core, an Interrupt Acknowledge cycle begins. The interrupt vector will be based on the
highest priority interrupt request active at this time.
12. t
44
is only required to determine when the Interrupt Acknowledge cycle will occur.
13. Interrupt requests should be held active until the Interrupt Acknowledge cycle for that interrupt occurs.
FIGURE 6. INTERRUPT TIMING: WITH INTERRUPT SUPPRESSION
FIGURE 7. INTERRUPT TIMING: WITH NO INTERRUPT SUPPRESSION
Timing Diagrams
(Continued)
MA
INTA
INTSUP
PCLK
e
1
e
2
e
3
e
4
e
5
t
44
t
46
t
47
t
46
t
47
t
67
t
68
t
28
t
26
EI
INT VECTOR
e
1
e
2
e
4
e
5
t
44
t
46
t
47
t
67
t
68
t
26
t
28
MA
INTA
INTSUP
PCLK
EI
INT VECTOR
HS-RTX2010RH
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