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參數資料
| 型號： | HS-RTX2010RH |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened Real Time Express⑩ Microcontroller |
| 中文描述： | 輻射加固實時快遞⑩微控制器 |
| 文件頁數： | 7/36頁 |
| 文件大小： | 406K |
| 代理商： | HS-RTX2010RH |
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7
NOTES:
5. If both LDS and UDS are low, no memory access is taking place in the current cycle. This only occurs during streamed instructions that do not
access memory.
6. During a streamed single cycle instruction, the Memory Data Bus is driven by the processor.
FIGURE 4. MEMORY BUS TIMING
NOTES:
7. GIO remains high for internal ASIC bus cycles.
8. GR/W goes low and GD is driven for all ASIC write cycles, including internal ones.
9. During non-ASIC write cycles, GD is not driven by the HS-RTX2010RH. Therefore, it is recommended that all GD pins be pulled to VCC or GND
to minimize power supply current and noise.
10. t
40B
and t
41B
specifications are for Streamed Mode of operation only.
FIGURE 5. ASIC BUS TIMING
Timing Diagrams
(Continued)
t
26
t
28
t
31
t
35
t
29
t
32
t
34
t
33
PCLK
MA
MD
IN
MD
OUT
LDS
UDS
NEW
BOOT
MR/W
t
21
t
22
t
48
t
50
t
51
t
49
t
52
t
56
t
54
t
58
t
42
t
43
t
40A, B
t
41A, B
t
62
t
61
t
63
t
65
GA
PCLK
ICLK
GIO
GR/W
GD
IN
GD
OUT
t
69
HS-RTX2010RH
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