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參數(shù)資料
| 型號(hào)： | HS-RTX2010RH |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened Real Time Express⑩ Microcontroller |
| 中文描述： | 輻射加固實(shí)時(shí)快遞⑩微控制器 |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 406K |
| 代理商： | HS-RTX2010RH |
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16
Dual Stack Architecture
The HS-RTX2010RH features a dual stack architecture. The
two 256-word stacks are the Parameter Stack and the
Return Stack, both of which may be accessed in parallel by a
single instruction, and which minimize overhead in passing
parameters between subroutines. The functional structure of
each of these stacks is shown in Figure 22.
The Parameter Stack is used for temporary storage of data
and for passing parameters between subroutines. The top two
elements of this stack are contained in the
registers of the processor, and the remainder of this stack is
located in stack memory. The stack memory assigned to the
Parameter Stack is 256 words deep by 16 bits wide.
and
The Return Stack is used for storing return addresses when
performing Subroutine Calls, or for storing values temporarily.
Because the HS-RTX2010RH uses a separate Return Stack, it
can call and return from subroutines and interrupts with a
minimum of overhead. The Return Stack is 21 bits wide. The
16-bitIndexRegister,
,andthe5-bitIndexPageRegister,
, hold the top element of this stack, while the remaining
elements are located in stack memory. The stack memory
portion of the Return Stack is 21 bits wide, by 256 words deep.
The data on the Return Stack takes on different meaning,
depending upon whether the Return Stack is being used for
temporary storage of data or to hold a return address during
a subroutine operation (Figure 19).
HS-RTX2010RH Stack Controllers
The two stacks of the HS-RTX2010RH are controlled by
identical Programmable Stack Controllers.
The operation of the Programmable Stack Controllers
depends on the contents of three registers. These registers
are
, the Stack Pointer Register,
Overflow Limit Register, and
Limit Register (see Figures 15, 16, and 17).
, the Stack
, the Stack Underflow
contains the address of the next stack memory
location to be accessed in a stack push (write) operation.
After a push, the
is incremented (post-increment
operation). In a stack pop (read) operation, the stack
memory location with an address one less than the
will be accessed, and then the
(pre-decrement operation). At start-up, the first stack
location to have data pushed into it is location zero.
Upper and lower limit values for the stacks are set into the
Stack Overflow Limit Register and in the Stack Underflow
Limit Register. These values allow interrupts to be generated
prior to the occurrence of stack overflow or underflow error
conditions (see section on Stack Error Conditions for more
detail). Since the HS-RTX2010RH can take up to four clock
cycles to respond to an interrupt, the values set in these
registers should include a safety margin which allows valid
stack operation until the processor executes the interrupt
service routine.
TOP
NEXT
I
IPR
SPR
SVR
SUR
SPR
SPR
SPR
SPR
(ON-CHIP)
STACK MEMORY
PARAMETER STACK
8
9
10
11
12
0
7
5
6
1
2
3
4
13
14
15
8
9
10
11
12
0
7
5
6
1
2
3
4
13
14
15
RETURN STACK
(ON-CHIP)
STACK MEMORY
RVL
PVL
RSU
RSP
1
2
8
9
0
1 0
2
3
4
5
6
7
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
0
1
2
I
IPR
PSU
PSP
TOP
NEXT
8
SVR
9
10
11
12
13
14
15
0
7
5
6
1
2
3
4
8
9
10
11
12
13
14
15
0
7
5
6
1
2
3
4
SPR
8
9
10
11
12
13
14
15
0
7
5
6
1
2
3
4
SUR
FIGURE 22. DUAL STACK ARCHITECTURE
HS-RTX2010RH
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