參數(shù)資料
型號(hào)： HS-RTX2010RH
廠商： Intersil Corporation
英文描述： Radiation Hardened Real Time Express⑩ Microcontroller
中文描述： 輻射加固實(shí)時(shí)快遞⑩微控制器
文件頁(yè)數(shù)： 23/36頁(yè)
文件大小： 406K
代理商： HS-RTX2010RH
23
Interrupt Controller. The SWI is reset by executing an
instruction that clears the flip-flop. The flip-flop is accessed
by I/O Reads and Writes.
Because the SWI interrupt may not be serviced immediately,
the instructions which immediately follow the SWI instruction
should not depend on whether or not the interrupt has been
serviced, and should cause a one or two-cycle idle condition
(Typically, this is done with one or two NOP instructions).
If an interrupt condition occurs, but “goes away” before the
processor has a chance to service it, a “No Interrupt” vector is
generated. A “No Interrupt” vector is also generated if an
Interrupt Acknowledge cycle takes less than two cycles to
execute and no other interrupt conditions need to be serviced.
To prevent unforeseen errors, it is recommended that valid
code be supplied at every Interrupt Vector location, including
the “No Interrupt” vector, which should always be initialized
with valid code.
It is recommended that Interrupt Handlers save and restore
the contents of
.
CR
Interrupt Suppression
The HS-RTX2010RH allows maskable interrupts and Mode
1 NMIs (the NMI_MODE Flag in bit 11 of the
be suppressed, delaying them temporarily while critical
operations are in progress. Critical operations are instruction
sequences and hardware operations that, if interrupted,
would result in the loss of data or misoperation of the
hardware. (Note: Only the processor may suppress NMIs.)
is set) to
Standard critical operations during which interrupts are
automatically suppressed by the processor include Streamed
instructions (see the description of the
sequences (see “Subroutine Calls and Returns”), and loading
. In addition to this, external devices can also suppress
maskable interrupts during critical operations by applying a
HIGH level on the INTSUP pin for as long as required.
register), Long Call
Since the Mode 0 NMI (the NMI_MODE Flag in bit 11 of the
is cleared) can cause the processor to perform an
Interrupt Acknowledge Cycle in the middle of these critical
operations, thereby preventing a normal return to the
interrupted instruction, a Subroutine Return should be used
with care from a Mode 0 NMI service routine. The Mode 0
NMI should be used only to indicate critical system errors,
and the Mode 0 NMI handler should re-initialize the system.
Interrupts which have occurred while interrupt suppression is
in effect will be recognized on a priority basis as soon as the
suppression terminates, provided the condition which
generated the interrupt still exists.
Stack Error Interrupts
The Stack Controllers request an interrupt whenever a stack
overflow or underflow condition exists. These interrupts can
be cleared by rewriting
. See the section on “Dual
SPR
Stack Architecture” for more information regarding how the
limits set into
and
IBC
SUR
are used.
Stack Overflow:
A stack overflow occurs when data is
pushed onto the stack location pointed to by the
determined in Table 5. After the processor is reset, this is
location 255 in either the Parameter Stack or Return Stack.
A stack overflow interrupt request stays in effect until cleared
by writing a new value to the
an interrupt, the state of the stack overflow flags may be
read out of the
, bit 3 for the Parameter Stack, and bit
4 for the Return stack. See Figures 13, 15 and 16.
, as
. In addition to generating
Stack Underflow:
The stack underflow limit occurs when
data is popped off the stack location immediately below that
pointed to by the
, as determined in Table 2. The state
of the stack underflow error flags may be read out of bits 1
and 2 of the
for the Parameter and Return stacks
respectively. In the reset state of the
be generated at the same time that a fatal error is detected.
An underflow buffer region can be set up by selecting an
underflow limit greater than zero by writing the
corresponding value into the
interrupt request stays in effect until a new value is written
into the
, at which time it is cleared.
SPR
, an underflow will
. The stack underflow
Timer/Counter Interrupts
The timers generate edge-sensitive interrupts whenever they
are decremented to 0. Because they are edge-sensitive and
are cleared during an Interrupt Acknowledge cycle or during
the direct reading of
by software, no action is required
by the handlers to clear the interrupt request.
The HS-RTX2010RH ALU
The HS-RTX2010RH has a 16-bit ALU capable of
performing standard arithmetic and logic operations:
ADD and SUBTRACT (A-B and B-A; with and without
carry)
AND, OR, XOR, NOR, NAND, XNOR, NOT
The
shifts in the same cycle as a logic or arithmetic operation.
and
registers can also undergo single bit
NEXT
In Figure 24, the control and data paths to the ALU are
shown. Except for
and
core registers can be addressed explicitly, as can other
internal registers in special operations such as in Step
instructions. In each of these cases, the input would be
addressed as a device on the ASIC Bus.
, each of the internal
When executing these instructions, the arithmetic/logic
operand (a) starts out in
Operand (b) arrives at the ALU on the Y-bus, but can come
from one of the following four sources:
register; an ASIC Bus device; or from the 5 least significant
bits of
. The source of operand (b) is determined by
the instruction code in
. The result of the ALU
operation is placed into
TOP
and is placed on the T-bus.
; an internal
.
CR
I
CR
CR
SVR
SPR
IBC
SUR
IBC
SUR
SUR
IVR
TOP
TOP
NEXT
TOP
NEXT
IR
IR
HS-RTX2010RH
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