參數(shù)資料
型號： HPC3130APBM
廠商： Texas Instruments, Inc.
英文描述： PCI Bus Interface/Controller
中文描述： PCI總線接口/控制器
文件頁數(shù)： 15/41頁
文件大小： 537K
代理商： HPC3130APBM
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
slot control and status functions (continued)
TERMINAL
NO.
120
NAME
NO.
128
NO.
144
I/O
FUNCTION
PWRON/OFF[3]
PWRON/OFF[2]
PWRON/OFF[1]
PWRON/OFF[0]
109
91
71
52
116
98
76
55
130
109
86
61
O
Power ON/OFF. This output is provided per slot and is driven to the power switch to control
the slot power state.
REQ64ON[3]
REQ64ON[2]
REQ64ON[1]
REQ64ON[0]
116
98
78
59
123
105
83
62
137
119
93
70
O
CBT switch control for SLOTREQ64. A CBT switch can be implemented to reduce trace
loading of the additional REQ64 signal inherent to the HPC3130A controller. This output
can be used to control the CBT switch. This output is only driven by the HPC3130A under
programmed control.
REQ64ON[3]
REQ64ON[2]
REQ64ON[1]
REQ64ON[0]
118
99
80
60
125
106
85
63
140
120
95
72
O
CBT switch control for SLOTREQ64. A CBT switch can be implemented to reduce trace
loading of the additional REQ64 signal inherent to the HPC3130A controller. This output
can be used to control the CBT switch. This output is only driven by the HPC3130A under
programmed control.
SLOTREQ64[3]
SLOTREQ64[2]
SLOTREQ64[1]
SLOTREQ64[0]
7
8
9
10
8
9
10
11
10
11
12
13
O
Slot request 64. This output is driven in conjunction with SLOTRST to the hot-plug slot to
indicate to option cards whether or not they are plugged into a 64-bit slot. If a 64-bit device
is plugged into a 32-bit slot, then it must ensure that its high-word path inputs do not
oscillate and that there is not a significant power drain through the input buffer. This output
is only driven by the HPC3130A under programmed control.
SLOTRST[3]
SLOTRST[2]
SLOTRST[1]
SLOTRST[0]
115
97
77
58
122
104
82
61
136
118
92
68
O
Slot PCI reset. This output is driven to the hot-plug slot to reset it after power up. When a
card is inserted into a hot-plug slot it must be reset independent of the other PCI devices on
the bus. This output is only driven by the HPC3130A under programmed control.
HPC3130A applications
This section discusses the various features of the HPC3130A in detail, and presents design considerations
including a general connection sequencing guideline.
system implementation
Figure 1 illustrates the HPC3130A implementation. The PCI bus signals are switched to the hot–plug PCI slot
by the BUSON output, which controls a CBT switch. The PCI clock, PCI reset, M66EN, and REQ64 must not
be routed through the CBT switch. The HPC3130A drives the slot PCI reset and SLOTREQ64, which can be
controlled by internal HPC3130A registers. The SLOTREQ64 requires special consideration during reset, as
described. The PCI clock to the slot is driven by a clock driver, which is enabled by the HPC3130A CLKON
output.
The HPC3130A also provides other features such as mechanical detection circuits, attention indicators, and
interrupt signaling. The mechanical detection circuitry using the DETECT[1,0] inputs is displayed as a dotted
line and is an optional feature. Two attention indicator outputs, ATTN[1,0], are provided: one indicator to draw
the attention of the user to a particular slot for insertion/removal, and one optional indicator that can be used
to indicate fault conditions. Additional features, such as 66-MHz capability and automatic sequencing, are
discussed in the following sections.
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