參數(shù)資料
型號： HPC167064EL20
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： High-Performance microController with a 16k UV Erasable CMOS EPROM
中文描述： UVPROM, MICROCONTROLLER, CQCC68
封裝： WINDOWED, LDCC-68
文件頁數(shù)： 30/34頁
文件大?。?/td> 415K
代理商： HPC167064EL20
30 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and
Figures 1 thru 5 ) VCC e 5V g10% TA e 0 Cto a70 C for HPC467064
Symbol and Formula
Parameter
Min
Max
Units
Notes
fC
CKI Operating Frequency
2
30
MHz
tC1 e 1fC
CKI Clock Period
33
500
ns
tCKIH
CKI High Time
225
ns
tCKIL
CKI Low Time
225
ns
tC e 2fC
CPU Timing Cycle
66
ns
tWAIT e tC
CPU Wait State Period
66
ns
tDC1C2R
Delay of CK2 Rising Edge after CKI Falling Edge
0
55
ns
(Note 2)
tDC1C2F
Delay of CK2 Falling Edge after CKI Falling Edge
0
55
ns
(Note 2)
fU e fC 8
External UART Clock Input Frequency
375
MHz
fMW
External MICROWIREPLUS Clock Input Frequency
1875
MHz
fXIN e fC 22
External Timer Input Frequency
1364
MHz
tXIN e tC
Pulse Width for Timer Inputs
66
ns
tUWS
MICROWIRE Setup TimeMaster
100
ns
MICROWIRE Setup TimeSlave
20
tUWH
MICROWIRE Hold TimeMaster
20
ns
MICROWIRE Hold TimeSlave
50
tUWV
MICROWIRE Output Valid TimeMaster
50
ns
MICROWIRE Output Valid TimeSlave
150
tSALE e
tC a 40
HLD Falling Edge before ALE Rising Edge
90
ns
tHWP e tC a 10
HLD Pulse Width
76
ns
tHAE e tC a 85
HLDA Falling Edge after HLD Falling Edge
151
ns
(Note 3)
tHAD e
tC a 85
HLDA Rising Edge after HLD Rising Edge
135
ns
tBF e
tC a 66
Bus Float after HLDA Falling Edge
99
ns
(Note 5)
tBE e
tC a 66
Bus Enable after HLDA Rising Edge
99
ns
(Note 5)
tUAS
Address Setup Time to Falling Edge of URD
10
ns
tUAH
Address Hold Time from Rising Edge of URD
10
ns
tRPW
URD Pulse Width
100
ns
tOE
URD Falling Edge to Output Data Valid
0
60
ns
tOD
Rising Edge of URD to Output Data Invalid
5
45
ns
(Note 6)
tDRDY
RDRDY Delay from Rising Edge of URD
70
ns
tWDW
UWR Pulse Width
40
ns
tUDS
Input Data Valid before Rising Edge of UWR
10
ns
tUDH
Input Data Hold after Rising Edge of UWR
20
ns
tA
WRRDY Delay from Rising Edge of UWR
70
ns
tDC1ALER
Delay from CKI Rising Edge to ALE Rising Edge
0
35
ns
(Notes 1 2)
tDC1ALEF
Delay from CKI Rising Edge to ALE Falling Edge
0
35
ns
(Notes 1 2)
tDC2ALER e
tC a 20
Delay from CK2 Rising Edge to ALE Rising Edge
37
ns
tDC2ALEF e
tC a 20
Delay from CK2 Falling Edge to ALE Falling Edge
37
ns
tLL e
tC b 9
ALE Pulse Width
24
ns
tST e
tC b 7
Setup of Address Valid before ALE Falling Edge
9
ns
tVP e
tC b 5
Hold of Address Valid after ALE Falling Edge
11
ns
Clocks
Timers
MicrowirePlus
External
Hold
UPI
Timing
Address
Cycles
5
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