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參數(shù)資料
| 型號： | HPC-DEV-WDBC |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | High-Performance microController with A/D |
| 中文描述： | 高性能微控制器/數(shù) |
| 文件頁數(shù)： | 2/39頁 |
| 文件大?。?/td> | 430K |
| 代理商： | HPC-DEV-WDBC |
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Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Total Allowable Source or Sink Current
100 mA
Storage Temperature Range
b
65
§
C to
a
150
§
C
Lead Temperature (Soldering, 10 sec.)
300
§
C
V
CC
with Respect to GND
All Other Pins
b
0.5V to 7.0V
(V
CC
a
0.5)V to (GND
b
0.5)V
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings.
DC Electrical Characteristics
V
CC
e
5.0V
g
10% unless otherwise specified, T
A
e
0
§
C to
a
70
§
C for HPC46164/HPC46104,
b
40
§
C to
a
85
§
C for
HPC36164/HPC36104
Symbol
Parameter
Test Conditions
Min
Max
Units
I
CC1
Supply Current
V
CC
e
5.5V, f
in
e
30 MHz (Note 1)
V
CC
e
5.5V, f
in
e
20 MHz (Note 1)
V
CC
e
5.5V, f
in
e
2.0 MHz (Note 1)
V
CC
e
5.5V, f
in
e
30 MHz (Note 1)
V
CC
e
5.5V, f
in
e
20 MHz (Note 1)
V
CC
e
5.5V, f
in
e
2.0 MHz (Note 1)
V
CC
e
5.5V, f
in
e
0 kHz (Note 1)
V
CC
e
2.5V, f
in
e
0 kHz (Note 1)
65
mA
47
mA
10
mA
I
CC2
IDLE Mode Current
5
mA
3
mA
1
mA
I
CC3
HALT Mode Current
300
m
A
100
m
A
INPUT VOLTAGE LEVELS FOR SCHMITT TRIGGERED INPUTS RESET, NMI, WO; AND ALSO CKI
V
IH1
Logic High
0.9 V
CC
V
V
IL1
Logic Low
0.1 V
CC
V
ALL OTHER INPUTS
V
IH2
Logic High (except Port D)
0.7 V
CC
V
V
IL2
Logic Low (except Port D)
0.2 V
CC
V
V
IH3
Logic High (Port D Only)
(Note 9 in AC Characteristics)
0.7 V
CC
V
V
IL3
Logic Low (Port D Only)
(Note 9 in AC Characteristics)
0.2 V
CC
V
I
LI1
Input Leakage Current
V
IN
e
0 and V
IN
e
V
CC
V
IN
e
0
RESET
e
0, V
IN
e
V
CC
g
2
b
50
m
A
I
LI2
Input Leakage Current RDY/HLD, EXUI
b
3
m
A
I
LI3
Input Leakage Current B12
0.5
7
m
A
C
I
Input Capacitance
(Note 2)
10
pF
C
IO
I/O Capacitance
(Note 2)
20
pF
OUTPUT VOLTAGE LEVELS
V
OH1
Logic High (CMOS)
I
OH
e b
10
m
A (Note 2)
I
OH
e
10
m
A (Note 2)
I
OH
e b
7 mA
I
OL
e
3 mA
I
OH
e b
1.6 mA (except WO)
I
OL
e
0.5 mA
I
OH
e b
6 mA
I
OL
e
1.6 mA
I
OH
e b
1 mA
I
OL
e
3 mA
V
CC
b
0.1
V
V
OL1
Logic Low (CMOS)
0.1
V
V
OH2
Port A/B Drive, CK2
(A
0
–A
15
, B
10
, B
11
, B
12
, B
15
)
2.4
V
V
OL2
0.4
V
V
OH3
Other Port Pin Drive, WO (open
drain) (B
0
–B
9
, B
13
, B
14
, P
0
–P
3
)
2.4
V
V
OL3
0.4
V
V
OH4
ST1 and ST2 Drive
2.4
V
V
OL4
0.4
V
V
OH5
Port A/B Drive (A
0
–A
15
, B
10
, B
11
, B
12
, B
15
) When
Used as External Address/Data Bus
2.4
V
V
OL5
0.4
V
V
RAM
RAM Keep-Alive Voltage
TRI-STATE
é
Leakage Current
(Note 3)
2.5
V
CC
V
I
OZ
V
IN
e
0 and V
IN
e
V
CC
g
5
m
A
Note 1:
I
CC1
, I
CC2
, I
CC3
measured with no external drive (I
OH
and I
OL
e
0, I
IH
and I
IL
e
0). I
CC1
is measured with RESET
e
GND. I
CC3
is measured with NMI
e
V
CC
and A/D inactive. CKI driven to V
IH1
and V
IL1
with rise and fall times less than 10 ns. V
REF
e
AGND
e
GND.
Note 2:
This is guaranteed by design and not tested.
Note 3:
Test duration is 100 ms.
2
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