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參數(shù)資料
| 型號(hào)： | HPC-DEV-SYS4 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | High-Performance microController with A/D |
| 中文描述： | 高性能微控制器/數(shù) |
| 文件頁(yè)數(shù)： | 5/39頁(yè) |
| 文件大?。?/td> | 430K |
| 代理商： | HPC-DEV-SYS4 |
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A/D Converter Specifications
V
CC
e
5V
g
10% (V
SS
b
0.05V)
s
Any Input
s
(V
CC
a
0.05V), f
C
e
20 MHz and Prescalar
e
f
C
/12.
Parameter
Conditions
Min
Typ
Max
Units
Resolution
8
Bits
Reference Voltage Input
AGND
e
0V
3
V
CC
V
Absolute Accuracy
V
CC
e
5.5V, V
REF
e
5V,
V
CC
e
5V, V
REF
e
5V and
V
CC
e
4.5V, V
REF
e
4.5V
g
2
LSB
Non-Linearity
V
CC
e
5.5V, V
REF
e
5V,
V
CC
e
5V, V
REF
e
5V and
V
CC
e
4.5V, V
REF
e
4.5V
g
(/2
LSB
Differential Non-Linearity
V
CC
e
5.5V, V
REF
e
5V,
V
CC
e
5V, V
REF
e
5V and
V
CC
e
4.5V, V
REF
e
4.5V
g
(/2
LSB
Input Reference Resistance
1.6
4.8
k
X
Common Mode Input Range (Note 9)
AGND
V
REF
V
DC Common Mode Error
g
(/4
LSB
Off Channel Leakage Current
g
2
m
A
On Channel Leakage Current
g
2
m
A
A/D Clock Frequency (Note 8)
0.1
1.67
MHz
Conversion Time (Note 7)
12.5
A/D Clock Cycles
Note 7:
Conversion Time includes sample and hold time. See following diagrams.
Note 8:
See Prescalar description.
Note 9:
For V
IN(
b
)
l
V
IN(
a
)
the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input. The diodes will forward conduct for analog
input voltages below ground or above the V
CC
supply. Be careful, during testing at low V
CC
levels (4.5V), as high level analog inputs (5.0V) can cause this input
diode to conductDespecially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This
means that as long as the analog V
IN
does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 V
DC
to
5.0V
DC
input voltage range will therefore require a minimum supply voltage of 4.950 V
DC
over temperature variations, initial tolerance and loading.
Timing Diagram
TL/DD/9682–11
Note:
The trigger condition generated by the start conversion method selected by the SC bits requires one CK2 to propagate through before the trigger condition is
known. Once the trigger condition is known, the sample and hold will start at the next rising edge of ADCLK. The figure shows worst case.
5
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