參數(shù)資料
型號(hào)： HPC-DEV-SYS4
廠商： National Semiconductor Corporation
英文描述： High-Performance microController with A/D
中文描述： 高性能微控制器/數(shù)
文件頁(yè)數(shù)： 21/39頁(yè)
文件大小： 430K
代理商： HPC-DEV-SYS4
Timer Overview
The HPC46164 contains a powerful set of flexible timers
enabling the HPC46164 to perform extensive timer func-
tions not usually associated with microcontrollers. The
HPC46164 contains nine 16-bit timers. Timer T0 is a free-
running timer, counting up at a fixed CKI/16 (Clock Input/
16) rate. It is used for WATCHDOG logic, high speed event
capture, and to exit from the IDLE mode. Consequently, it
cannot be stopped or written to under software control. Tim-
er T0 permits precise measurements by means of the cap-
ture registers I2CR, I3CR, and I4CR. A control bit in the
register TMMODE configures timer T1 and its associated
register R1 as capture registers I3CR and I2CR. The cap-
ture registers I2CR, I3CR, and I4CR respectively, record the
value of timer T0 when specific events occur on the inter-
rupt pins I2, I3, and I4. The control register IRCD programs
the capture registers to trigger on either a rising edge or a
falling edge of its respective input. The specified edge can
also be programmed to generate an interrupt (see Figure
19 ).
TL/DD/9682–21
FIGURE 19. Timers T0, T1 and T8 with
Four Input Capture Registers
The HPC46164 provides an additional 16-bit free running
timer, T8, with associated input capture register EICR (Ex-
ternal Interrupt Capture Register) and Configuration Regis-
ter, EICON. EICON is used to select the mode and edge of
the EI pin. EICR is a 16-bit capture register which records
the value of T8 (which is identical to T0) when a specific
event occurs on the EI pin.
The timers T2 and T3 have selectable clock rates. The
clock input to these two timers may be selected from the
following two sources: an external pin, or derived internally
by dividing the clock input. Timer T2 has additional capabili-
ty of being clocked by the timer T3 underflow. This allows
the user to cascade timers T3 and T2 into a 32-bit timer/
counter. The control register DIVBY programs the clock in-
put to timers T2 and T3 (see Figure 20 ).
The timers T1 through T7 in conjunction with their registers
form Timer-Register pairs. The registers hold the pulse du-
ration values. All the Timer-Register pairs can be read from
or written to. Each timer can be started or stopped under
software control. Once enabled, the timers count down, and
upon underflow, the contents of its associated register are
automatically loaded into the timer.
SYNCHRONOUS OUTPUTS
The flexible timer structure of the HPC46164 simplifies
pulse generation and measurement. There are four syn-
chronous timer outputs (TS0 through TS3) that work in con-
junction with the timer T2. The synchronous timer outputs
can be used either as regular outputs or individually pro-
grammed to toggle on timer T2 underflows (seeFigure 20 ).
TL/DD/9682–22
FIGURE 20. Timers T2–T3 Block
21
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