參數(shù)資料
型號: HPC-DEV-ISE2-E
廠商: National Semiconductor Corporation
英文描述: High-Performance Communications MicroController
中文描述: 高性能通信微控制器
文件頁數(shù): 4/30頁
文件大?。?/td> 362K
代理商: HPC-DEV-ISE2-E
AC Electrical Characteristics
(Continued)
CPU and DMA Timing (see Notes 1 and 4 and Figures 2, 4, 6, 7, 8, and 9), V
CC
e
5V
g
10%, T
A
e
0
§
C to
a
70
§
C for
HPC46400E,
b
40
§
C to
a
85
§
C for HPC36400E
Symbol
Formula
Cycle
Parameter
Min
Max
Units
Note
t
1ALR
CPU
DMA
Delay of ALE Rising Edge after CKI Rising Edge
Delay of ALE Rising Edge after CKI Falling Edge
0
0
35
35
ns
ns
(Note 2)
(Note 2)
t
1ALF
CPU
DMA
Delay of ALE Falling Edge after CKI Rising Edge
Delay of ALE Falling Edge after CKI Falling Edge
0
0
35
35
ns
ns
(Note 2)
(Note 2)
t
2ALR
(/4
t
C
a
20
(/4
t
C
a
20
(/2
t
C
b
9
(/4
t
C
b
20
(/4
t
C
b
10
(/2
t
C
b
10
(/2
t
C
b
20
t
C
a
WS
b
55
±/4
t
C
a
WS
b
75
(/4
t
C
a
WS
b
35
(/2
t
C
a
WS
(/4
t
C
a
WS
b
15
(/2
t
C
a
WS
b
15
*/4
t
C
b
25
*/4
t
C
b
20
(/2
t
C
b
20
*/4
t
C
a
WS
b
15
(/2
t
C
a
WS
b
15
(/2
t
C
a
WS
b
40
(/2
t
C
a
WS
b
50
(/4
t
C
b
10
CPU
ALE Rising Edge after CK2 Rising Edge
45
ns
t
2ALF
CPU
ALE Falling Edge after CK2 Falling Edge
45
ns
t
LL
ALE Pulse Width
41
ns
t
ST
Setup of Address Valid before ALE Falling Edge
5
ns
(Note 3)
t
VP
CPU
DMA
Hold of Address Valid after ALE Falling Edge
15
40
ns
ns
t
ARR
ALE Falling Edge to RD Falling Edge
30
ns
t
ACC
CPU
DMA
Data Input Valid after Address Output Valid
145
150
ns
ns
t
RD
CPU
DMA
Data Input Valid after RD Falling Edge
90
115
ns
ns
t
RW
CPU
DMA
RD Pulse Width
110
135
ns
ns
t
DR
Hold of Data Input Valid after RD Rising Edge
0
50
ns
t
RDA
Bus Enable after RD Rising Edge
55
ns
t
ARW
ALE Falling Edge to WR Falling Edge
30
ns
t
WW
CPU
DMA
WR Pulse Width
160
135
ns
ns
t
V
CPU
DMA
Data Output Valid before WR Rising Edge
110
100
ns
ns
t
HW
Hold of Data Output Valid after WR Rising Edge
15
ns
(Note 5)
t
RDYS
RDY Falling Edge before CK2 Rising Edge
45
ns
t
RDYH
RDY Rising Edge after CK2 Rising Edge
0
ns
t
RDYV
WS
b
(/4
t
C
b
47
t
C
b
47
CPU
DMA
RDY Falling Edge after RD or WR Falling Edge
28
53
ns
ns
(Note 6)
A
R
W
R
I
Note 1:
These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO. Spec’d t
C1R
, t
C1F
,
and CKI duty cycle limits are not tested but are guaranteed functional by design. Keep in mind that when SLOW mode is selected, f
C
(Operating Frequency) will be
the external frequency divided by 4 and that value should be used in all formulas relating to the AC Characteristics.
Note 2:
Do not design with this parameter unless CKI is driven with an active signal meeting T
C1R
and T
C1F
specs. When using a passive crystal circuit, its stability
is not guaranteed if either CKI or CKO is connected to any external logic other than the passive components of the crystal circuit.
Note 3:
Setup of HBE valid before ALE falling edge is 0 ns minimum. Setup of BS0 thru BS3 valid before ALE falling edge when in extended addressing mode is
0 ns minimum.
Note 4:
WS (t
WAIT
)
c
(number of preprogrammed wait states). Minimum and maximum values are calculated at maximum operating frequency, f
C
e
20 MHz, with
one wait state preprogrammed. These values are guaranteed with AC loading of 100 pF on Port A, 50 pF on CK2, 80 pF on other outputs, and DC loading of the
pin’s DC spec non CMOS I
OL
or I
OH
.
Note 5:
Hold of HBE Output Valid after WR rising edge is 0 ns minimum. Hold of BS0 thru BS3 Output Valid after WR rising edge when in extended addressing
mode is 0 ns minimum.
Note 6:
In HPC in-circuit emulators the t
RDYV
formulas are WS
b
(/4
t
C
b
57 and t
C
b
57 yielding minimums of 18 ns and 43 ns for CPU and DMA cycles,
respectively.
4
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