參數(shù)資料
型號: HPC-DEV-ISE2-E
廠商: National Semiconductor Corporation
英文描述: High-Performance Communications MicroController
中文描述: 高性能通信微控制器
文件頁數(shù): 16/30頁
文件大小: 362K
代理商: HPC-DEV-ISE2-E
MICROWIRE/PLUS Operation
The HPC46400E can enter the MICROWIRE/PLUS mode
as the master or a slave. A control bit in the IRCD register
determines whether the HPC46400E is the master or slave.
The shift clock is generated when the HPC46400E is config-
ured as a master. An externally generated shift clock on the
SK pin is used when the HPC46400E is configured as a
slave. When the HPC46400E is a master, the DIVBY regis-
ter programs the frequency of the SK clock. The DIVBY
register allows the SK clock frequency to be programmed in
14 selectable steps from 122 Hz to 1 MHz with CKI at
16 MHz.
The contents of the SIO register may be accessed through
any of the memory access instructions. Data waiting to be
transmitted in the SIO register is shifted out on the falling
edge of the SK clock. Serial data on the SI pin is latched in
on the rising edge of the SK clock.
HPC46400E UART
The HPC46400E contains a software programmable UART.
The UART (seeFigure 16) consists of a transmit shift regis-
ter, a receiver shift register and five addressable registers,
as follows: a transmit buffer register (TBUF), a receiver buff-
er register (RBUF), a UART control and status register
(ENU), a UART receive control and status register (ENUR)
and a UART interrupt and clock source register (ENUI). The
ENU register contains flags for transmit and receive func-
tions; this register also determines the length of the data
frame (7, 8 or 9 bits) and the value of the ninth bit in trans-
mission. The ENUR register flags framing, parity, and data
overrun errors while the UART is receiving. Other functions
of the ENUR register include saving the ninth bit received in
the data frame, reporting receiving and transmitting status,
and enabling or disabling the UART’s Wake-up Mode of op-
eration. The determination of an internal or external clock
source is done by the ENUI register, as well as selecting the
number of stop bits (
-/8
, 1, 1
-/8
, 2), selecting between the
synchronous or asynchronous mode and enabling or dis-
abling transmit and receive interrupts.
The clock inputs to the Transmitter and Receiver sections
of the UART can be individually selected to come from ei-
ther an off-chip source on the CKX pin or one of the three
on-chip sources. Presently, two of the on-chip sources, the
Divide-By (DIVBY) Register and the Precision UART Timer
(PUT), are primarily for reasons of upward compatibility from
earlier HPC family members. The most flexible and accurate
on-chip clocking is provided by the third source: the Baud
Rate Generator (BRG).
The Baud Rate Generator is controlled by the register pair
PSR and BAUD, shown below.
The Prescaler factor is selected by the upper 5 bits of the
PSR register (the PRESCALE field), in units of the CK2
clock from 1 to 16 in
(/2
step increments. The lower 3 bits of
the PSR register, in conjunction with the 8 bits of the baud
register, form the 11-bit BAUDRATE field, which defines a
baud rate divisor ranging from 1 to 2048, in units of the
prescaled clock selected by the PRESCALE field.
In Asynchronous Mode, the resulting baud rate is
(/16
of the
clocking rate selected through the BRG circuit. The maxi-
mum baud rate generated using the BRG is 625 kbaud.
In the Synchronous Mode data is transmitted on the rising
edge and received on the falling edge of the external clock.
Although the data is transmitted and received synchronous-
ly, it is still contained within an asynchronous frame; i.e., a
start bit, parity bit (if selected) and stop bit(s) are still pres-
ent.
TL/DD/10422–25
FIGURE 16. UART Block Diagram
TL/DD/10422–26
UART Baud Rate Generator (BRG) Registers PSR and BAUD
16
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HPC-DEV-SYS2-E CABLE, COAX, RG179, BROWN, 3MM, 25M; Length, Reel (Imperial):82ft; Attenuation, 400MHz:68.90dB; Capacitance:75pF/m; Conductor make-up:7/0.102 mm; Diameter, External:3.00mm; Impedance:75R; Length, Reel (Metric):25m; Resistance, per RoHS Compliant: Yes
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