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參數(shù)資料
| 型號： | HN29W25611T |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 256M AND type Flash Memory More than 16,057-sector (271,299,072-bit) |
| 中文描述： | 256M超過16057型快閃記憶體部門（271299072位） |
| 文件頁數(shù)： | 6/42頁 |
| 文件大?。?/td> | 331K |
| 代理商： | HN29W25611T |
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HN29W25611T-50H
6
Pin Function
CE
:
CE
is used to select the device. The status returns to the standby at the rising edge of
CE
in the reading
operation. However, the status does not return to the standby at the rising edge of
CE
in the busy state in
programming and erase operation.
OE
:
Memory data and status register data can be read, when
OE
is V
IL
.
WE
:
Commands and address are latched at the rising edge of
WE
.
SC:
Programming and reading data is latched at the rising edge of SC.
RES
:
RES
pin must be kept at the V
ILR
(V
SS
±
0.2 V) level when V
CC
is turned on and off. In this way, data
in the memory is protected against unintentional erase and programming.
RES
must be kept at the V
IHR
(V
CC
±
0.2 V) level during any operations such as programming, erase and read.
CDE
:
Commands and data are latched when
CDE
is V
IL
and address is latched when
CDE
is V
IH
.
RDY/
Busy
:
The RDY/
Busy
indicates the program/erase status of the flash memory. The RDY/
Busy
signal
is initially at a high impedance state. It turns to a V
OL
level after the (40H) command in programming
operation or the (B0H) command in erase operation. After the erase or programming operation finishes, the
RDY/
Busy
signal turns back to the high impedance state.
I/O0 to I/O7:
The I/O pins are used to input data, address and command, and are used to output memory data
and status register data.
Mode Selection
Mode
CE
OE
WE
SC
RES
CDE
RDY/
Busy
*
3
I/O0 to I/O7
Deep standby
×
*
4
×
×
×
×
×
×
×
×
V
ILR
V
IHR
V
IHR
V
IHR
V
IHR
×
×
×
×
V
OH
V
OH
V
OH
V
OH
V
OH
High-Z
Standby
V
IH
V
IL
V
IL
V
IL
High-Z
Output disable
V
IH
V
IL
V
IH
V
IH
V
IH
V
IL
High-Z
Status register read*
1
Status register outputs
Command write*
2
Notes: 1. Default mode after the power on is the status register read mode (refer to status transition). From
I/O0 to I/O7 pins output the status, when
CE
= V
IL
and
OE
= V
IL
(conventional read operation
condition).
2. Refer to the command definition. Data can be read, programmed and erased after commands are
written in this mode.
3. The RDY/
Busy
bus should be pulled up to V
CC
to maintain the V
OH
level while the RDY/
Busy
pin
outputs a high impedance.
4. An
×
means “Don’t care”. The pin level can be set to either V
IL
or V
IH
referred to DC characteristics.
V
IL
V
IL
Din
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PDF描述 |
|---|---|
| HN29W25611T-50H | 256M AND type Flash Memory More than 16,057-sector (271,299,072-bit) |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HN29W25611T-50 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:256M AND type Flash Memory More than 16,057-sector (271,299,072-bit) |
| HN29W25611T-50H | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:256M AND type Flash Memory More than 16,057-sector (271,299,072-bit) |
| HN29W256H02TE-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| HN29W256SH02TE-1 | 制造商:Renesas Electronics Corporation 功能描述:256M FLASH CONTROLLER - Trays |
| HN29W3221T-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AND Flash EEPROM |
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