參數(shù)資料
型號： HMP8115CN
廠商： INTERSIL CORP
元件分類： 顏色信號轉(zhuǎn)換
英文描述： NTSC/PAL Video Decoder
中文描述： COLOR SIGNAL DECODER, PQFP80
封裝： 20 X 14 MM, PLASTIC, QFP-80
文件頁數(shù)： 9/43頁
文件大?。?/td> 183K
代理商： HMP8115CN
9
BUILT-IN VIDEO GENERATION
When the blue screen, black screen or color bar output is
selected, a full-screen of blue, black or 75% colorbar output
is generated using the currently selected output format. The
type of screen to be generated is determined by bits 2 and 1
of the OUTPUT FORMAT register 02
H
. When built-in video
generation is not desired, the bits need to be set for normal
operation to pass decoded video.
If a video source is input, it will be used to provide the video
timing. If an input video source is not detected, internally-
generated video timing will be used.
Pixel Port Timing
The the timing and format of the output data and control sig-
nals is presented in the following sections.
HSYNC AND VSYNC TIMING
The HSYNC and VSYNC output timing is VMI v1.4 compati-
ble. Figures 5-8 illustrate the video timing. The leading edge
of HSYNC is synchronous to the video input signal and has
a fixed latency due to internal pipeline processing. The pulse
width of the HSYNC is defined by the END HSYNC register
36H, where the trailing edge of HSYNC has a programmable
delay of 0-510 CLK2 cycles from the leading edge.
The leading edge of VSYNC is asserted approximately half
way through the first serration pulse of each field. For an odd
field, the trailing edge of VSYNC is 5
±
1 CLK2 cycles after
the trailing edge of the HSYNC that follows the last equaliza-
tion pulse. Refer to Figures 5 and 7. For an even field, the
trailing edge of VSYNC is 5
±
1 CLK2 cycles leading the lead-
ing edge of the HSYNC that follows the last equalization
pulse. Refer to Figures 6 and 8.
FIELD TIMING
When field information can be determined from the input
video source, the FIELD output pin reflects the video source
field state. When field information cannot be determined
from the input video source, the FIELD output pin alternates
its state at the beginning of each field. FIELD changes state
5
±
1 CLK2 cycles before the leading edge of VSYNC.
VIDEO
INPUT
VSYNC
FIELD
‘EVEN’ FIELD
NOTE:
3. The trailing edge of VSYNC is 5
±
1 clocks after the trailing edge of HSYNC to be VMI compatible and to indicate a transition to an odd field.
FIGURE 5. NTSC(M) AND PAL(M) HSYNC, VSYNC AND FIELD TIMING DURING AN EVEN TO ODD FIELD TRANSITION
‘ODD’ FIELD
HSYNC
523
PAL(M)
LINE #
524
525
1
2
3
4
5
6
7
522
521
1
NTSC(M)
LINE #
2
3
4
5
6
7
8
9
10
525
524
NOTE:
4. The trailing edge of VSYNC is 5
±
1 clocks after the leading edge of HSYNC to be VMI compatible and to indicate a transition to an even field.
FIGURE 6. NTSC(M) AND PAL(M) HSYNC, VSYNC AND FIELD TIMING DURING AN ODD TO EVEN FIELD TRANSITION
VIDEO
INPUT
VSYNC
FIELD
‘ODD’ FIELD
‘EVEN’ FIELD
HSYNC
261
PAL(M)
LINE #
262
263
264
265
266
267
268
269
270
260
259
264
NTSC(M)
LINE #
265
266
267
268
269
270
271
272
273
263
262
HMP8115
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HMP8116 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Decoder
HMP8116CN 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Decoder
HMP8117 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Decoder
HMP8117_07 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Decoder
HMP8117CN 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 80PQFP,0+70C NTSC/PAL VIDEO DECODER W/MA RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
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