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參數(shù)資料
| 型號： | HMP8115CN |
| 廠商： | INTERSIL CORP |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | 20 X 14 MM, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 21/43頁 |
| 文件大?。?/td> | 183K |
| 代理商： | HMP8115CN |
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21
Host Interface
All internal registers may be written to or read by the host
processor at any time, except for those bits identified as
read-only. The bit descriptions of the control registers are
listed in Tables 9-48.
The HMP8115 supports the fast-mode (up to 400 kbps) I
2
C
interface consisting of the SDA and SCL pins. The device
acts as a slave for receiving and transmitting data over the
serial interface. When the interface is not active, SCL and
SDA must be pulled high using external 4k
pull-up resis-
tors. The slave address for the HMP8115 is 88
H
.
Data is placed on the SDA line when the SCL line is low and
held stable when the SCL line is pulled high. Changing the
state of the SDA line while SCL is high will be interpreted as
either an I
2
C bus START or STOP condition as indicated by
Figure 20.
During I
2
C write cycles, the first data byte after the slave
address is treated as the control register sub address and is
written into the internal address register. Any remaining data
bytes sent during an I
2
C write cycle are written to the control
registers, beginning with the register specified by the
address register as given in the first byte. The address regis-
ter is then autoincremented after each additional data byte
sent on the I
2
C bus during a write cycle. Writes to reserved
bits within registers or reserved registers are ignored.
In order to perform a read from a specific control register
within the HMP8115, an I
2
C bus write must first be per-
formed to properly setup the address register. Then an I
2
C
bus read can be performed to read from the desired control
register(s). As a result of needing the write cycle for a read
cycle there are actually two START conditions as shown in
Figure 21. The address register is then autoincremented
after each byte read during the I
2
C read cycle. Reserved
registers return a value of
00
H
.
FIGURE 19. I
2
C TIMING DIAGRAM
SDA
SCL
t
BUF
t
LOW
t
HIGH
t
R
t
F
t
SU:DATA
t
HD:DATA
t
SU:STOP
SDA
SCL
START
CONDITION
S
1-7
ADDRESS
8
R/W
9
ACK
1-7
DATA
8
9
ACK
STOP
CONDITION
P
FIGURE 20. I
2
C SERIAL DATA FLOW
S = START CYCLE
P = STOP CYCLE
A = ACKNOWLEDGE
NA = NO ACKNOWLEDGE
FROM MASTER
FROM HMP8115
0x88
DATA WRITE
DATA
DATA
0x88
DATA READ
0x89
1000 1000 (R/W)
1000 1000
FIGURE 21. REGISTER WRITE/READ FLOW
S
CHIP ADDR
A
SUB ADDR
DATA
DATA
P
NA
CHIP ADDR
S
SUB ADDR
CHIP ADDR
S
P
A
A
A
A
A
A
REGISTER
POINTED
TO BY
SUB ADDR
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
A
REGISTER
POINTED
TO BY
SUB ADDR
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
HMP8115
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PDF描述 |
|---|---|
| HMR100 | Hadware Manual |
| HMR-100 | Hadware Manual |
| HMS188CWHRLP-20 | x8 SRAM |
| HMS188CS-15 | x8 SRAM |
| HMS188CS-20 | x8 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMP8116 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Decoder |
| HMP8116CN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Decoder |
| HMP8117 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Decoder |
| HMP8117_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Decoder |
| HMP8117CN | 功能描述:編碼器、解碼器、復用器和解復用器 80PQFP,0+70C NTSC/PAL VIDEO DECODER W/MA RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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