參數(shù)資料
型號(hào): HMMC-5025
元件分類: 放大器
英文描述: 2000 MHz - 50000 MHz RF/MICROWAVE WIDE BAND LOW POWER AMPLIFIER
封裝: 0.0677 X 0.0362 INCH, DIE
文件頁(yè)數(shù): 1/8頁(yè)
文件大小: 111K
代理商: HMMC-5025
Avago HMMC-5025
2 – 50 GHz Distributed Amplifier
Data Sheet
Description
The HMMC-5025 was designed as a generic wide band
distributed amplifier, covering the frequency span 2–
50 GHz. It consists of seven stages. Each stage is made
up of two cascoded FETs with gate peripheries of 48
m per FET. Both input and output ports were
designed to provide 50 Ohm terminations. Bonding
pads are provided in the layout to allow amplifier
operation at frequencies lower than 2 GHz by means
of external circuit components.
The amplifier is biased with a single positive drain
supply (V
DD) and a single negative gate supply (VG1).
A second date connection is provided for external
gain control applications.
Features
Frequency range:
2 – 50 GHz
Small signal gain:
8.5 dB
P-1dB @ 40 GHz:
12 dBm
Noise figure:
5 dB @ 2 – 35 GHz
7 dB @ 35 – 50 GHz
Return loss:
In/Out: < -10 dB
30 dB gain control
Absolute Maximum Ratings[1]
Symbol
Parameters/Conditions
Units
Min.
Max.
VDD
Positive Drain Voltage
V
7.0
IDD
Total Drain Current
mA
170
V
G1
First Gate Voltage
V
-3.5
0
VG2
Second Gate Voltage
V
-3.0
+3.0
PDC
DC Power Dissipation
watts
1.2
Pin
CW Input Power
dBm
20
Tch
Operating Channel Temp.
°C
150
T
case
Operating Case Temperature
°C
-55
Tstg
Storage Temperature
°C
-65
+165
Tmax
Max. Assembly Temp.
°C
300
(for 60 seconds max.)
Notes:
1. Operation in excess of any one of these conditions may result in
permanent damage to this device. T
A = 25°C except for T
ch, TSTG, and Tmax.
Chip Size:
1720 x 920
m (67.7 x 36.2 mils)
Chip Size Tolerance:
±10 m (±0.4 mils)
Chip Thickness:
127
± 15 m (5.0 ± 0.6 mils)
Pad Dimensions:
80 x 80
m (3.2 x 3.2 mils)
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