參數(shù)資料
型號: HM51W18165LJ-7
廠商: Hitachi,Ltd.
英文描述: 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh
中文描述: 16米EDO公司的DRAM(1 - Mword 16位)4畝刷新/ 1畝刷新
文件頁數(shù): 5/36頁
文件大?。?/td> 461K
代理商: HM51W18165LJ-7
HM51W16165 Series, HM51W18165 Series
5
Block Diagram
(HM51W16165 Series)
A0
A1
to
A7
A10
A11
A8
A9
Timing and control
RAS
UCAS
LCAS
WE
OE
Column
address
buffers
Row
address
buffers
I/O buffers
I/O0
to
I/O15
Column decoder
R
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
Block Diagram
(HM51W18165 Series)
A0
A1
to
A9
Timing and control
Column
address
buffers
Row
address
buffers
I/O buffers
I/O0
to
I/O15
Column decoder
R
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
RAS
UCAS
LCAS
WE
OE
Truth Table
This Material Copyrighted By Its Respective Manufacturer
相關(guān)PDF資料
PDF描述
HM51W18165J-6 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh
HM51W16165J-7 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh
HM51W18165J-7 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh
HM5212325FBPC-B60 128M LVTTL interface SDRAM 100 MHz 1-Mword x 32-bit x 4-bank PC/100 SDRAM
HM5212325FBPC 128M LVTTL interface SDRAM(128M LVTTL 接口同步DRAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM51W18165LTT6 制造商:HITACHI 功能描述:*
HM51W4260CLTT-6 制造商:Hitachi 功能描述:
HM5212165/2805 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Series 128M LVTTL Interface SDRAM 66 MHz 2-Mword X 16-Bit X4-Bank
HM5212165D/2805D 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Series 128M LVTTL Interface SDRAM 100 MHz 2-Mword X 16-Bit X 4-
HM5212165D/2805D-B60 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128M LVTTL Interface SDRAM 100 MHz 2-Mword X 16-Bit X 4-Ban