參數(shù)資料
型號: HM5164165FLJ-5
廠商: Hitachi,Ltd.
英文描述: 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
中文描述: 6400 EDO公司的DRAM(4 Mword x 16位)8K的refresh/4k刷新
文件頁數(shù): 7/37頁
文件大?。?/td> 510K
代理商: HM5164165FLJ-5
HM5164165F Series, HM5165165F Series
7
Operation Table
RAS
LCAS
UCAS
WE
OE
I/O 0 to I/O 7
I/O 8 to I/O 15 Operation
H
×
×
×
×
High-Z
High-Z
Standby
L
L
H
H
L
Dout
High-Z
Read cycle
L
H
L
H
L
High-Z
Dout
L
L
L
H
L
Dout
Dout
L
L
H
L*
2
×
×
×
Din
×
Early write cycle
L
H
L
L*
2
×
Din
L
L
L
L*
2
Din
Din
L
L
H
L*
2
H
Din
×
Delayed write cycle
L
H
L
L*
2
H
×
Din
L
L
L
L*
2
H
Din
Din
L
L
H
H to L
L to H
Dout/Din
High-Z
Read-modify-write cycle
L
H
L
H to L
L to H
High-Z
Dout/Din
L
L
L
H to L
L to H
Dout/Din
Dout/Din
L
H
H
×
×
×
×
×
High-Z
High-Z
RAS
-only refresh cycle
CAS
-before-
RAS
refresh cycle or
H to L
H
L
H
High-Z
High-Z
H to L
L
H
H
High-Z
High-Z
Self refresh cycle (L-version)
H to L
L
L
H
High-Z
High-Z
L
Notes: 1. H: V
IH
(inactive) L: V
IL
(active)
×
: V
IH
or V
IL
2. t
WCS
0 ns: Early write cycle
t
WCS
< 0 ns: Delayed write cycle
3. Mode is determined by the OR function of the
UCAS
and
LCAS
. (Mode is set by the earliest of
UCAS
and
LCAS
active edge and reset by the latest of
UCAS
and
LCAS
inactive edge.) However
write operation and output High-Z control are done independently by each
UCAS
,
LCAS
.
ex. if
RAS
= H to L,
LCAS
= L,
UCAS
= H, then
CAS
-before-
RAS
refresh cycle is selected.
L
L
H
H
High-Z
High-Z
Read cycle (Output disabled)
相關(guān)PDF資料
PDF描述
HM5164165FLJ-6 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
HM5164165FTT-5 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
HM5165165FTT-5 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
HM5164165FTT-6 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
HM5165165FTT-6 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
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