參數(shù)資料
型號： HM5164165FLJ-5
廠商： Hitachi,Ltd.
英文描述： 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
中文描述： 6400 EDO公司的DRAM（4 Mword x 16位）8K的refresh/4k刷新
文件頁數(shù)： 17/37頁
文件大?。?/td> 510K
代理商： HM5164165FLJ-5
HM5164165F Series, HM5165165F Series
17
16.t
RASP
defines
RAS
pulse width in EDO page mode cycles.
17.Access time is determined by the longest among t
AA
, t
CAC
and t
CPA
.
18.In delayed write or read-modify-write cycles,
OE
must disable output buffer prior to applying data to
the device.
19.When output buffers are enabled once, sustain the low impedance state until valid data is obtained.
When output buffer is turned on and off within a very short time, generally it causes large V
CC
/V
SS
line noise, which causes to degrade V
IH
min/V
IL
max level.
20.t
(min) can be achieved during a series of EDO page mode write cycles or EDO page mode read
cycles. If both write and read operation are mixed in a EDO page mode
RAS
cycle (EDO page
mode mix cycle (1), (2)), minimum value of
CAS
cycle (t
+ t
+ 2 t
) becomes greater than the
specified t
(min) value.The value of
CAS
cycle time of mixed EDO page mode is shown in EDO
page mode mix cycle (1) and (2).
21.Data output turns off and becomes high impedance from later rising edge of
RAS
and
CAS
. Hold
time and turn off time are specified by the timing specifications of later rising edge of
RAS
and
CAS
between t
OHR
and t
OH
, and between t
OFR
and t
OFF
.
22.t
defines the time at which the output level go cross. V
OL
= 0.8 V, V
OH
= 2.0 V of output timing
reference level.
23.Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64 ms
period on the condition a and b below.
a. Enter self refresh mode within 15.6
μ
s after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within
15.6
μ
s after exiting from self refresh mode.
24.In case of entering from
RAS
-only-refresh, it is necessary to execute CBR refresh before and after
self refresh mode according as note 23.
25 At t
> 100
μ
s, self refresh mode is activated, and not activated at t
< 10
μ
s. It is undefined
within the range of 10
μ
s
≤
t
RASS
≤
100
μ
s. For t
RASS
≥
10
μ
s, it is necessary to satisfy t
RPS
.
26.When both
UCAS
and
LCAS
go low at the same time, all 16-bit data are written into the device.
UCAS
and
LCAS
cannot be staggered within the same write/read cycles.
27.t
ASC
, t
CAH
, t
RCS
, t
WCS
, t
WCH
, t
CSR
and t
RPC
are determined by the earlier falling edge of
UCAS
or
LCAS
.
28.t
CRP
, t
CHR
, t
RCH
, t
CPA
and t
CPW
are determined by the later rising edge of
UCAS
or
LCAS
.
29.t
CWL
, t
DH
, t
DS
and t
CHS
should be satisfied by both
UCAS
and
LCAS
.
30.t
CP
is determined by the time that both
UCAS
and
LCAS
are high.
31.XXX: H or L (H: V
IH
(min)
≤
V
IN
≤
V
IH
(max), L: V
IL
(min)
≤
V
IN
≤
V
IL
(max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied V
IH
or V
IL
.
相關(guān)PDF資料
PDF描述
HM5164165FLJ-6 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
HM5164165FTT-5 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
HM5165165FTT-5 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
HM5164165FTT-6 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
HM5165165FTT-6 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM5165165FTT-60 制造商:Hitachi 功能描述:
HM51680J 制造商:TT Electronics / BI Technologies 功能描述:Ind Power Wirewound 68uH 5% 1KHz 3.3A AXL
HM51-680J 制造商:BI Technologies (TT electronics) 功能描述:Ind Power Wirewound 68uH 5% 1KHz 3.3A AXL
HM51-680JLF 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Axially Leaded Miniature Power Inductors
HM51680K 制造商:TT Electronics / BI Technologies 功能描述:Ind Power Wirewound 68uH 10% 1KHz 3.3A AXL
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