results. For example, with f
參數(shù)資料
型號: HI7190IBZ-T
廠商: Intersil
文件頁數(shù): 15/25頁
文件大?。?/td> 0K
描述: IC ADC 24BIT PROGBL SER 20-SOIC
產(chǎn)品培訓(xùn)模塊: Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 24
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 32.5mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,單極;1 個差分,雙極
22
FN3612.10
June 27, 2006
result in conversion X + 1 data overwriting conversion X
results. For example, with fOSC = 10MHz, fN = 2kHz, the
read cycle must start within 1/2000 - 128(1/106) = 487
μs
after DRDY went low.
2) The Data Output Register read cycle for conversion X
must be completed within 2(1/fN)-1440(1/fOSC) after DRDY
initially goes active low. If the read cycle for conversion X is
not complete within this time the results of conversion X + 1
are lost and results from conversion X + 2 are now stored in
the data output word buffer.
Completing the Data Output Register read cycle inactivates
the DRDY interrupt. If the one word data output buffer is full
when this read is complete this data will be immediately
transferred to the Data Output Register and a new DRDY
interrupt will be issued after the minimum DRDY pulse high
time is met.
Writing the Control Register
If data is written to byte 2 and/or byte 1 of the Control
Register the DRDY output is taken high and the device re-
calibrates if written to a calibration mode. This action is taken
because it is assumed that by writing byte 2 or byte 1 that
the user either reprogrammed the filter or changed modes of
the part. However, if a single data byte is written to byte 0, it
is assumed that the gain has NOT been changed. It is up to
the user to re-calibrate the HI7190 after the gain has been
changed by this method. It is recommended that the entire
Control Register be written to when changing the selected
gain. This ensures that the part is re-calibrated before the
DRDY signal goes low indicating valid data is available.
Offset Calibration Register
The Offset Calibration Register is a 24-bit register containing
the offset correction factor. This register is indeterminate on
power-up but will contain a Self Calibration correction value
after a RESET has been applied.
The Offset Calibration Register holds the value that corrects
the filter output data to all 0’s when the analog input is 0V.
Positive Full Scale Calibration Register
The Positive Full Scale Calibration Register is a 24-bit
register containing the Positive Full Scale correction
coefficient. This coefficient is used to determine the positive
gain slope factor. This register is indeterminate on power-up
but will contain a Self Calibration correction coefficient after
a RESET has been applied.
Negative Full Scale Calibration Register
The Negative Full Scale Calibration Register is a 24-bit
register containing the Negative Full Scale correction
coefficient. This coefficient is used to determine the negative
gain slope factor. This register is indeterminate on power-up
but will contain a Self Calibration correction coefficient after
a RESET has been applied.
BYTE 2
MSB
22212019181716
O23
O22
O21
O20
O19
O18
O17
O16
BYTE 1
15
14
13
12
11
10
9
8
O15
O14
O13
O12
O11
O10
O9
O8
BYTE 0
7654321
LSB
O7
O6
O5
O4
O3
O2
O1
O0
BYTE 2
MSB
22212019181716
P23
P22
P21P20
P19P18
P17P16
BYTE 1
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
BYTE 0
7654321
LSB
P7
P6
P5
P4
P3
P2
P1
P0
BYTE 2
MSB
22212019181716
N23
N22
N21
N20
N19
N18
N17
N16
BYTE 1
15
14
13
12
11
10
9
8
N15
N14
N13
N12
N11
N10
N9
N8
BYTE 0
7654321
LSB
N7
N6
N5
N4
N3
N2
N1
N0
HI7190
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