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參數資料
| 型號： | HI7188IP |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System |
| 中文描述： | 8-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP40 |
| 文件頁數： | 11/22頁 |
| 文件大小： | 156K |
| 代理商： | HI7188IP |
7-1857
Analog Inputs
The analog inputs on the HI7188 are fully differential inputs
with programmable gain capabilities. The inputs accept both
unipolar and bipolar input signals and gains of 1, 2, 4 or 8.
The gain for any given physical channel is independent of
the gain of other physical channels. The gain is programmed
via the Channel Configuration Register (CCR).
The input impedance of the HI7188 is dependent upon the
modulator input sampling capacitors which varies with the
selected PGIA gain. Table 2 shows the sampling capacitors
and input impedances for the different gain settings of the
HI7188. Note that this table is valid only for a 3.6864MHz
master clock. If the input clock frequency is changed then
the input impedance will change accordingly. The equation
used to calculate the input impedance is
Where C
S
is the internal sampling capacitance and F
S
is the
modulator sampling rate set by the master clock divided by
six (F
S
= 3.6864MHz/6 = 614.4kHz).
(RESET) INITIAL SYSTEM START
APPLY A ZERO SCALE INPUT
TO EACH OF THE CHANNELS
PROGRAM THE SYSTEM LEVEL
INFORMATION IN THE
CONTROL REGISTER (CR)
PROGRAM THE CHANNEL LEVEL
INFORMATION IN THE
CHANNEL CONFIGURATION
REGISTERS (CCR)
AND PLACE EACH CHANNEL
IN OFFSET CALIBRATION MODE
APPLY A POSITIVE FULL SCALE INPUT
TO EACH CHANNEL
REPROGRAM THE CCR
TO PLACE EACH CHANNEL IN
POSITIVE FULL SCALE
CALIBRATION MODE
APPLY A NEGATIVE FULL SCALE
INPUT TO EACH CHANNEL
REPROGRAM THE CCR
TO PLACE EACH CHANNEL IN
NEGATIVE FULL SCALE
CALIBRATION MODE
CA OUTPUT
INTERRUPT ACTIVE
YES
NO
CA OUTPUT
INTERRUPT ACTIVE
YES
NO
CA OUTPUT
INTERRUPT ACTIVE
YES
NO
CONNECT DESIRED ANALOG INPUT,
READ DATA RAM VIA
SERIAL INTERFACE
RECALIBRATION REQUIRED
NO
YES
EOS OUTPUT
INTERRUPT ACTIVE
NO
YES
FIGURE 7. SYSTEM USAGE FLOWCHART
TABLE 2. EFFECTIVE INPUT IMPEDANCE vs GAIN
GAIN
SAMPLING
RATE
(kHz)
SAMPLING
CAPACITOR
(pF)
INPUT
IMPEDANCE
(k
)
1
614.4
4
407
2
614.4
8
203
4
614.4
16
102
8
614.4
32
51
4TH
ORDER
∑
MODULATOR
CONVERSION
CONTROL
V
IN1H
V
IN2H
V
IN3H
V
IN4H
V
IN5H
V
IN6H
V
IN7H
V
IN8H
V
IN1L
V
IN2L
V
IN3L
V
IN4L
V
IN5L
V
IN6L
V
IN7L
V
IN8L
PGIA
V
RHI
V
RLO
V
CM
PHYSICAL
CHANNELS
DIGITAL
SECTION
REFERENCE INPUTS
FIGURE 8. ANALOG BLOCK DIAGRAM
Z
IN
= 1/(C
S
x F
S
)
HI7188
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