參數(shù)資料
型號(hào)： HI7188IN
廠商： HARRIS SEMICONDUCTOR
元件分類： ADC
英文描述： 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System
中文描述： 8-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQFP44
文件頁(yè)數(shù)： 16/22頁(yè)
文件大?。?/td> 156K
代理商： HI7188IN
7-1862
When the range detection logic determines an over range,
the converter output will clamp at the >(V
PFS
- 1.5 LSB) out-
put as described in Tables 4 and 5. When the range detec-
tion logic determines an under range, the converter output
will clamp at the <(V
NFS
+ 0.5 LSB) output described in
Table 4 or the <(V
ZS
+ 0.5 LSB) output described in Table 5.
Data RAM
The Data RAM block is comprised of two 8 x 16 memory ele-
ments which store conversion results after calibration and
data coding. Two RAMs are required to allow a one channel
scan buffer per logical channel. The user can only READ from
the data RAM. For illustration, these elements are labeled
RAM0 and RAM1. The RAMs are configured such that when
one is internally writable the other is readable via serial I/O.
The following paragraphs describe the data RAM operation.
Please refer to the Functional Block Diagram.
For example, from initialization, RAM0 is writable, RAM1 is
readable, EOS is inactive. Conversion completes on all
active logical channels (RAM0 stores conversion N data)
and the EOS interrupt is generated. Internally, the microse-
quencer switches RAM0 to readable, RAM1 to writable. The
user can read the data RAM to obtain N conversion results,
clearing the EOS interrupt.
The next conversion N+1 completes on all active logical
channels (RAM1 stores N+1 data). If a data RAM (RAM0
containing N data) read has been completed before the N+1
conversion scan has completed, RAM1 will switch to being
readable and RAM0 is writable. This is normal operation and
no conversion results are lost.
If the data RAM (RAM0 containing N data) is not completely
read before the N+1 conversion is completed, there are two
possible results.
1. The data RAM read has not been started (RAM0 containing
N data), EOS remains active low and the microsequencer
will switch RAM1 to be readable and RAM0 to be writable.
This has the effect of overwriting conversion N with N+2.
2. The data RAM (RAM0 containing N data) read has been
started but is not complete, the read pointer remains with
RAM0 and the write pointer remains with RAM1. This has
the effect of overwriting conversion N+1 with N+2 before
N+1 can be read, therefore conversion N+1 is lost.
Clocking/Oscillators
The master clock of the HI7188 can be supplied by either a
crystal connected between the OSC
1
and OSC
2
pins as
shown in Figure 13A or a CMOS compatible clock signal
connected to the OSC
1
pin as shown in Figure 13B and
floating the OSC
2
pin. The master clock is used by the inter-
nal clock generator to derive the clock edges required for
both analog and digital sections. The HI7188 is designed or
a 3.6864MHz clock to maintain Line Noise Rejection.
Crystal Operation
Using a crystal to generate the clock, care must be taken to
minimize any external stray capacitance/inductance seen by
the OSC
1
and OSC
2
pins. If care is not taken, the feedback
(crystal) loop noise will result in a non reliable master clock,
which in turn, will produce erroneous conversion results. The
crystal should be connected as close to the HI7188 device
as physically possible. If you cannot meet these require-
ments, we would recommend you use an External CMOS
Clock instead of the crystal.
External CMOS Clock Operation
When driving the HI7188 with an external CMOS clock, the
clock should never be turned off. If the clock is turned off, the
device should be re-synchronized by resetting either manually
via the RESET pin or by the following special software instruc-
tions. If the device is not re-synchronized erroneous conver-
sion results may be observed. The hardware reset will clear all
registers and RAMs as defined in the data sheet. The software
reset is achieved by either performing an I/O access of any
calibration RAM or cycling the device through a sleep cycle.
Calibration RAM Access
To re-synchronize the conversion process the user may per-
form an I/O access of any calibration RAM (read or write).
When the user performs this I/O access the microsequencer
stops the conversion process, resets the modulator, digital
filter and waits until the I/O is complete. After the I/O is com-
pleted the microsequencer automatically restarts the conver-
sion process.
Sleep Cycle
Another method to re-synchronize the conversion process is
to cycle the device through a sleep cycle. The user places
the device in SLEEP mode by writing the SLP bit (CR<3>) of
the Control Register to logic one. The microsequencer will
stop the conversion process, reset the conversion pointer to
logical channel one, clear the four line noise rejection filters
and deactivate EOS. The serial interface, calibration/data
RAMs, CR and CCR are not affected.
To return from sleep mode the user changes the SLP bit
from high to low. This restarts the conversion process begin-
ning with logical channel 1. If line noise rejection (LNR) is
enabled, it takes four complete scans (all eight channels) to
TABLE 4. BIPOLAR MODE OUTPUT CODES (HEX)
INPUT VOLTAGE
TWO’S
COMPLEMENT
CODE
OFFSET
BINARY CODE
>(V
PFS
- 1.5 LSB)
V
PFS
- 1.5 LSB
V
ZS
- 0.5 LSB
V
NFS
+ 0.5 LSB
<(V
NFS
+ 0.5 LSB)
7FFF
FFFF
7FFF/7FFE
FFFF/FFFE
0000/FFFF
8000/7FFF
8001/8000
0001/0000
8000
0000
TABLE 5. UNIPOLAR MODE DATA OUTPUT CODES (HEX)
INPUT VOLTAGE
BINARY CODE
>(V
PFS
- 1.5 LSB)
V
PFS
- 1.5 LSB
V
PFS
/2 - 0.5 LSB
V
ZS
+ .5 LSB
<(V
ZS
+ 0.5 LSB)
FFFF
FFFF/FFFE
8000/7FFF
0001/0000
0000
HI7188
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