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參數(shù)資料
| 型號： | HI7188IN |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System |
| 中文描述： | 8-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQFP44 |
| 文件頁數(shù)： | 14/22頁 |
| 文件大?。?/td> | 156K |
| 代理商： | HI7188IN |
7-1860
A one channel example:
1. Channel 1 is sampled four times as labeled S1, S2, S3,
and S4 in Figure 12. One sample for each 90 degrees
quadrant of line cycle (quarter main cycle).
2. Each sample is equally spaced (From zero, S1 = 5 degrees,
S2 = 95 degrees, S3 = 185 degrees and S4 = 275 degrees).
3. Each sample is of the same duration of time.
4. Samples S1 and S3 (180 degrees later) will have the
equal magnitudes of line noise but have opposite signs.
5. Samples S2 and S4 (180 degrees later) will have the
equal magnitudes but opposite signs.
6. The HI7188 sums the samples S1, S3, S2 and S4 which
results in averaging the line noise signal to zero.
7. These four samples are placed, real time, in the 4x8 array
of registers used for LNR. The next quadrant sampled (S5)
replaces S1 in the running average. The new sample re-
placed S1 at the same point on the line cycle, 5 degrees
but 360 degrees later. The line noise summation is still ze-
ro. Now for every quarter main cycle thereafter, the LNR
will be updated and line noise free output will be available.
Calibration
Calibration is the process of adjusting the conversion data
based on known system offset and gain errors. For a com-
plete system calibration to occur, the on-chip microcontroller
must perform a three point calibration which involves record-
ing conversion results for three different input conditions -
“zero-scale,” “positive full-scale,” and “negative full-scale”.
With these readings, the HI7188 can null any system offset
errors and calculate the positive and negative gain slope fac-
tors for the transfer function of the system. It is imperative
that the zero-scale calibration be performed before either of
the gain calibrations. The order of the gain calibrations is not
important. Non-calibrated data can be obtained from the
device by writing 000000 (h) to the Offset Calibration Regis-
ter, 800000 (h) to the Positive Full Scale Calibration Regis-
ter, and 800000 (h) to the Negative Full Scale Calibration
Register. This sets the offset of the part to 0 and both the
positive and negative gain slope factors to 1.
A calibration routine should be initiated whenever there is a
change in the ambient operating temperature or supply
voltage. It should also be initiated if there is a change in the
gain, bipolar, or unipolar input range.
The user may choose to ignore data during calibration or
check whether any ACTIVE channel is in calibration. Bit 12,
the SE bit, of the Control Register offers capability to sup-
press the EOS interrupt during calibration. If the SE bit is
high the EOS interrupt will be suppressed if any active logi-
cal channel is in the calibration mode. If the SE bit is high
and no active logical channels are in the calibration mode
the EOS interrupt will function normally. If low, the suppress
EOS function is disabled. To check whether any logical
channel is in calibration the user can monitor the Calibration
Active (CA) output pin. The CA output pin is high when at
least one of the active logical channels are in calibration. If a
non active logical channel is in calibration the CA will not be
high. The user can monitor the CA pin to determine when all
active logical channels are calibrated.
NOTE: When the user accesses the calibration RAMs, via the Serial
Interface, the conversion process stops, resetting the modulator, in-
tegrating filter and clearing the EOS interrupt. When the calibration
RAM I/O operation is completed the device automatically restarts be-
ginning on logical channel 1. The contents of the CR and CCR are
not affected by this I/O.
Calibration Time
The calibration time varies depending several factors includ-
ing LNR (50Hz/60Hz) being enabled or disabled, and 2 point
calibration. Table 3 contains a summary of the conversion
time depending on these factors. Since line noise rejection is
a major factor this discussion is divided accordingly.
Line Noise Rejection On
When line noise rejection is enabled, it takes 4 conversion
scan periods to fill the averaging filters used for attenuating
the periodic line noise. A conversion scan involves convert-
ing all 8 logical channels at a rate dependent on whether
LNR is set to 50Hz or 60Hz. The scan period is 5ms
(1/200Hz) and 4.167ms (1/240Hz) respectively. The number
of active channels is not applicable in this calculation since
the microsequencer converts on ALL logical channels to
maintain LNR timing regardless of the number of user
defined active channels.
TIME
I
1
2
3
4
567
8
234
5
6
7
8
1
2
3
4
56
7 8
23
4
5
6
7
8
1
1
1/4 LINE NOISE
S1
S2
S3
S4
FIGURE 12. LINE NOISE CYCLE INCLUDING PATENTED TIME
SPACED INPUT SAMPLING
S5
TABLE 3. CALIBRATION TIME
LNR
LNR
FREQ
(Hz)
ACTIVE
CHANS
CAL
PNTS
EACH
CAL
POINT
(ms)
TOTAL
CAL
(ms)
On
50
n/a
2
20
40
On
50
n/a
3
20
60
On
60
n/a
2
16.7
33.3
On
60
n/a
3
16.7
50.0
Off
n/a
N
2
N (0.4803)
2N (0.4803)
Off
n/a
N
3
N (0.4803)
3N (0.4803)
NOTE: N is the number of active channels. Total Cal column as-
sumes zero switching time between calibration points.
HI7188
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