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參數(shù)資料
| 型號： | HI5828 |
| 廠商： | Intersil Corporation |
| 英文描述： | 12-Bit, 125+MSPS, CommLink⑩ Dual High Speed CMOS D/A (2.7V-5.5V) |
| 中文描述： | 12位，125 MSPS的，CommLink⑩雙路高速CMOS的D / A（為2.7V至5.5V） |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 119K |
| 代理商： | HI5828 |
5
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage D
VDD
to DGND . . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage A
VDD
to AGND . . . . . . . . . . . . . . . . . . +5.5V
Grounds, AGND TO DGND . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D11-D0, CLK, SLEEP). . . . . . . D
VDD
+ 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . .A
VDD
+ 0.3V
Analog Output Current (IOUTA/B, QOUTA/B) . . . . . . . . . . . . . 24mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range. . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(LQFP - Lead Tips Only)
θ
JA
(
o
C/W)
70
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
A
VDD
= D
VDD
= +5V (except where otherwise noted), V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All
Typical Values
PARAMETER
TEST CONDITIONS
T
A
= -40
o
C TO 85
o
C
UNITS
MIN
TYP
MAX
SYSTEM PERFORMANCE
Resolution
12
-
-
Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 8)
-2.0
±
0.75
+2.0
LSB
Differential Linearity Error, DNL
(Note 8)
-1.0
±
0.5
+1.0
LSB
Offset Error, I
OS
(Note 8)
-0.025
-
+0.025
% FSR
Offset Drift Coefficient
(Note 8)
-
0.1
-
ppm
FSR/
o
C
Full Scale Gain Error, FSE
With External Reference (Notes 2, 8)
-10
±
2
+10
% FSR
With Internal Reference (Notes 2, 8)
-10
±
1
+10
% FSR
Full Scale Gain Drift
With External Reference (Note 8)
-
±
50
-
ppm
FSR/
o
C
With Internal Reference (Note 8)
-
±
100
-
ppm
FSR/
o
C
Full Scale Output Current, I
FS
2
-
20
mA
Crosstalk
f
CLK
= 100MSPS, f
OUT
= 10MHz
-
85
-
dB
f
CLK
= 100MSPS, f
OUT
= 40MHz
-
64
-
dB
Gain Matching Between Channels
(DC Measurement)
As a percentage of Full Scale Range
-5
-
+5
% FSR
In dB Full Scale Range
-0.445
-
+0.420
dB FSR
Output Voltage Compliance Range
(Note 3, 8)
-0.3
-
1.25
V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f
CLK
(Note 3)
125
-
-
MHz
Output Settling Time, (t
SETT
)
±
0.05% (
±
2 LSB) (Note 8)
-
35
-
ns
Singlet Glitch Area (Peak Glitch)
R
L
= 25
(Note 8)
-
5
-
pVs
Output Rise Time
Full Scale Step
-
2.5
-
ns
Output Fall Time
Full Scale Step
-
2.5
-
ns
Output Capacitance
-
10
-
pF
Output Noise
IOUTFS = 20mA
-
50
-
pA/
√
Hz
IOUTFS = 2mA
-
30
-
pA/
√
Hz
HI5828
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