參數(shù)資料
型號(hào): HI5865IN
廠商: INTERSIL CORP
元件分類: ADC
英文描述: 12-Bit, 65 MSPS A/D Converter
中文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44
封裝: 10 X 10 MM, METRIC, PLASTIC, MO-108AA-2, QFP-44
文件頁數(shù): 1/2頁
文件大?。?/td> 29K
代理商: HI5865IN
1
Semiconductor
PRELIMINARY
June 1998
HI5865
12-Bit, 65 MSPS A/D Converter
Features
Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . 65 MSPS
Low Power at 65 MSPS . . . . . . . . . . . . . . . . . . . .450mW
Internal Sample and Hold
Fully Differential Architecture
Full Power Input Bandwidth . . . . . . . . . . . . . . . 250MHz
Low Data Latency
TTL Compatible Clock Input
CMOS Compatible Digital Data Outputs
Applications
Multichannel Digital Communication Receivers
Cellular/PCS Basestation Receivers
Undersampling Digital IF
Digital Subscriber Line (VDSL)
Medical Ultrasound
Reference Literature
- AN9214, Using Harris High Speed A/D Converters
Description
The HI5865 is a monolithic, 12-bit, 65 MSPS Analog-to-
Digital
Converter
fabricated
process. It is designed for high speed, high resolution appli-
cations where wide bandwidth, low power consumption and
excellent
SINAD
performance
250MHz full power input bandwidth and high frequency
accuracy, the converter is ideal for many types of
communication systems employing digital IF architectures.
in
an
advanced
CMOS
are
essential.
With
a
The HI5865 is designed with a fully differential pipelined
architecture using a front end differential-in-differential-out
Sample-and-Hold amplifier (S/H). The HI5865 has excellent
dynamic performance while consuming 450mW of power at
65 MSPS.
Data output latches are provided which present valid data to
the output bus with a low data latency of 9 clock cycles.
Pinout
HI5865 (MQFP)
TOP VIEW
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HI5865IN
-40 to 85
44 Ld MQFP
Q44.10x10
HI5865EVAL1
25
Evaluation Platform
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17
28
27
26
25
24
23
22
21
20
19
18
39 38 37 36 35 34
33
32
31
30
29
44 43 42 41 40
DV
CC
D
GND
A
GND
AV
CC
A
GND
AV
CC
AV
CC1
A
GND1
V
IN-
V
IN+
V
DC
D10
D9
D7
D
GND
DV
CC
D6
D5
D4
D3
D2
D8
V
R
V
R
D
G
D
C
D
G
D
C
N
N
D
D
N
C
D
G
D
G
D
G
D
C
D
G
D
G
D
G
D
C
D
N
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
Harris Corporation 1998
File Number
4538
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