- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371815 > HI5828 (Intersil Corporation) 12-Bit, 125+MSPS, CommLink⑩ Dual High Speed CMOS D/A (2.7V-5.5V) PDF資料下載
參數(shù)資料
| 型號： | HI5828 |
| 廠商： | Intersil Corporation |
| 英文描述： | 12-Bit, 125+MSPS, CommLink⑩ Dual High Speed CMOS D/A (2.7V-5.5V) |
| 中文描述： | 12位，125 MSPS的，CommLink⑩雙路高速CMOS的D / A（為2.7V至5.5V） |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 119K |
| 代理商： | HI5828 |
4
Pin Descriptions
PIN NO.
PIN NAME
PIN DESCRIPTION
11, 19, 26
AGND
Analog Ground.
13, 24
A
VDD
Analog Supply (+2.7V to +5.5V).
28
CLK
Clock Input. The master and slave latches shown in the functional block diagram are simple D-latches.
Input data to the DAC passes through the “master” latches when the clock is low and is latched into the
“master” latches when the clock is high. Data presented to the “slave” latch passes through when the
clock is logic high and is latched into the “slave” latches when the clock is logic low. Adequate setup time
must be allowed for the MSBs to pass through the thermometer decoder before the clock goes high. This
master-slave arrangement comprises an edge-triggered flip-flop, with the DAC being updated on the
rising clock edge. It is recommended that the clock edge be skewed such that setup time is larger than
hold time for optimum spectral performance.
27
DGND
Connect to Digital Ground.
10
D
VDD
Digital Supply (+2.7V to +5.5V).
20
FSADJ
Full Scale Current Adjust. Use a resistor to analog ground to adjust full scale output current. Full Scale
Output Current = 32 x V
FSADJ
/R
SET
. Where V
FSADJ
is the voltage at this pin. V
FSADJ
tracks the voltage
on the REFIO pin (refer to the functional block diagram); which is typically 1.2V if the internal reference
is used.
14, 23
ICOMP1, QCOMP1
Compensation Pin for Use in Reducing Bandwidth/Noise. Each pin should be individually decoupled to
AVDD with a 0.1
μ
F capacitor. To minimize crosstalk, the part was designed so that these pins
must
be
connected externally, ideally directly under the device packaging. The voltage on these pins is used to
drive the gates of the PMOS devices that make up the current cells. Only the ICOMP1 pin is driven and
therefore QCOMP1 needs to be connected to ICOMP1, but de-coupled separately to minimize crosstalk.
If placed equally close to both pins, then only one decoupling capacitor might be necessary.
12, 25
ICOMP2, QCOMP2
Compensation Pin for Internal Bias Generation. Each pin should be individually decoupled to AGND with
a 0.1
μ
F capacitor. The voltage generated at these pins represents the voltage used to supply power to
the switch drivers (refer to the functional block diagram) which is 2.0V nominal. This arrangement helps
to minimize clock feedthrough to the current cell transistors for reduced glitch energy and improved
spectral performance.
43-48, 1-6,
29-40
ID11-ID0, QD11-QD0 Digital Data Input Ports. Bit 11 is Most Significant Bit (MSB) and bit 0 is the Least Significant Bit (LSB).
15, 22
IOUTA, QOUTA
Current Outputs of the Device. Full scale output current is achieved when all input bits are set to binary 1.
16, 21
IOUTB, QOUTB
Complementary Current Outputs of the Device. Full scale output current is achieved on the
complementary outputs when all input bits are set to binary 0.
7, 8, 41, 42
N.C.
No Connection. Future LSBs for dual 14-bit DAC.
17
REFIO
Reference voltage input if Internal reference is disabled. The internal reference is not intended to drive an
external load. Use 0.1
μ
F cap to ground when internal reference is enabled.
18
REFLO
Reference Low Select. When the internal reference is enabled, this pin serves as the precision ground
reference point for the internal voltage reference circuitry and therefore needs to have a good connection
to analog ground to enable internal 1.2V reference. To disable the internal reference circuitry this pin
should be connected to A
VDD
.
9
SLEEP
Control Pin for Power-Down Mode. Sleep Mode is active high; connect to ground for Normal Mode. The
Sleep pin has internal 25
μ
A (nominal) active pulldown current.
HI5828
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI5860SOICEVAL1 | 12-Bit, 125MSPS, CommLinkTM High Speed D/A Converter |
| HI5860IA | CONNECTOR ACCESSORY |
| HI5860IB | CONNECTOR ACCESSORY |
| HI5865IN | 12-Bit, 65 MSPS A/D Converter |
| HI5865 | 12-Bit, 65 MSPS A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5828_01 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 125+MSPS, CommLink⑩ Dual High Speed CMOS D/A (2.7V-5.5V) |
| HI5828EVAL2 | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 HI5828 EVAL PL ATFORM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| HI5828IN | 功能描述:DAC DUAL 12BIT 130MHZ 48-LQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| HI5860 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 125MSPS, CommLinkTM High Speed D/A Converter |
| HI5860 WAF | 制造商:Intersil Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。