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參數(shù)資料
| 型號(hào)： | HI5805BIBZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | CONV A/D 12BIT 5MSPS 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 5M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 功率耗散（最大）： | 350mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，雙極 |
4
Analog Input Common Mode Voltage Range (VIN+ + VIN-)/2
Differential Mode (Note 2)
1
2.3
4
V
INTERNAL VOLTAGE REFERENCE
Reference Output Voltage, VROUT (Loaded)
-
3.5
-
V
Reference Output Current
-
1
mA
Reference Temperature Coefficient
-
200
-
ppm/oC
REFERENCE VOLTAGE INPUT
Reference Voltage Input, VRIN
-
3.5
-
V
Total Reference Resistance, RL
-
7.8
-
k
Reference Current
-
450
-
A
DC BIAS VOLTAGE
DC Bias Voltage Output, VDC
-
2.3
-
V
Max Output Current (Not To Exceed)
-
1
mA
DIGITAL INPUTS (CLK)
Input Logic High Voltage, VIH
2.0
-
V
Input Logic Low Voltage, VIL
-
0.8
V
Input Logic High Current, IIH
VCLK = 5V
-
10.0
A
Input Logic Low Current, IIL
VCLK = 0V
-
10.0
A
Input Capacitance, CIN
-
7
-
pF
DIGITAL OUTPUTS (D0-D11)
Output Logic Sink Current, IOL
VO = 0.4V (Note 2)
1.6
-
mA
DVCC3 = 3.0V, VO = 0.4V
-
1.6
-
mA
Output Logic Source Current, IOH
VO = 2.4V (Note 2)
-0.2
-
mA
DVCC3 = 3.0V, VO = 2.4V
-
-0.2
-
mA
Output Capacitance, COUT
-
5
-
pF
TIMING CHARACTERISTICS
Aperture Delay, tAP
-
5
-
ns
Aperture Jitter, tAJ
-
5
-
ps (RMS)
Data Output Delay, tOD
-
8
-
ns
Data Output Hold, tH
-
8
-
ns
Data Latency, tLAT
For a Valid Sample (Note 2)
-
3
Cycles
Clock Pulse Width (Low)
5MSPS Clock
90
100
110
ns
Clock Pulse Width (High)
5MSPS Clock
90
100
110
ns
POWER SUPPLY CHARACTERISTICS
Total Supply Current, ICC
VIN+ - VIN- = 2V
-
60
70
mA
Analog Supply Current, AICC
VIN+ - VIN- = 2V
-
46
-
mA
Digital Supply Current, DICC1
VIN+ - VIN- = 2V
-
13
-
mA
Output Supply Current, DICC2
VIN+ - VIN- = 2V
-
1
-
mA
Power Dissipation
VIN+ - VIN- = 2V
-
300
350
mW
Offset Error PSRR,
VOS
AVCC or DVCC = 5V ±5%
-
2
-
LSB
Gain Error PSRR,
FSE
AVCC or DVCC = 5V ±5%
-
30
-
LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock off (clock low, hold mode).
Electrical Specifications
AVCC = DVCC1 = DVCC2 = DVCC3 = +5.0V, fS = 5MSPS at 50% Duty Cycle, VRIN = 3.5V, CL = 10pF,
TA = -40
oC to 85oC, Differential Analog Input, Typical Values are Test Results at 25oC,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITION
HI5805BIB (-40oC TO 85oC)
UNITS
MIN
TYP
MAX
HI5805
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