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參數(shù)資料
| 型號： | HI5766KCB |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | ADC |
| 英文描述： | 10-Bit, 60 MSPS A/D Converter |
| 中文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 155K |
| 代理商： | HI5766KCB |
42
The performance of the ADC does not change significantly
with the value of the analog input common mode voltage.
A DC voltage source, V
DC
, equal to 3.2V (Typ), is made
available to the user to help simplify circuit design when using
an AC coupled differential input. This low output impedance
voltage source is not designed to be a reference but makes an
excellent DC bias source and stays well within the analog
input common mode voltage range over temperature.
For the AC coupled differential input (Figure 25) assume
the difference between V
REF
+, typically 2.5V, and V
REF
-,
typically 2V, is 0.5V. Full scale is achieved when the V
IN
and -V
IN
input signals are 0.5V
P-P
, with -V
IN
being
180 degrees out of phase with V
IN
. The converter will be
at positive full scale when the V
IN
+ input is at
V
DC
+ 0.25V and the V
IN
- input is at V
DC
- 0.25V (V
IN
+ -
V
IN
- = +0.5V). Conversely, the converter will be at
negative full scale when the V
IN
+ input is equal to V
DC
-
0.25V and V
IN
- is at V
DC
+ 0.25V (V
IN
+ - V
IN
- = -0.5V).
The analog input can be DC coupled (Figure 26) as long as
the inputs are within the analog input common mode voltage
range (0.25V
≤
VDC
≤
4.75V).
The resistors, R, in Figure 26 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from V
IN
+ to V
IN
- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
Analog Input, Single-Ended Connection
The configuration shown in Figure 27 may be used with a
single ended AC coupled input.
Again, assume the difference between V
REF
+, typically
2.5V, and V
REF
-, typically 2V, is 0.5V. If V
IN
is a 1V
P-P
sinewave, then V
IN
+ is a 1V
P-P
sinewave riding on a positive
voltage equal to VDC. The converter will be at positive full
scale when V
IN
+ is at VDC + 0.5V (V
IN
+ - V
IN
- = +0.5V)
and will be at negative full scale when V
IN
+ is equal to
VDC - 0.5V (V
IN
+ - V
IN
- = -0.5V). Sufficient headroom must
be provided such that the input voltage never goes above
+5V or below AGND. In this case, VDC could range between
0.5V and 4.5V without a significant change in ADC
performance. The simplest way to produce VDC is to use the
DC bias source, V
DC
, output of the HI5766.
The single ended analog input can be DC coupled
(Figure 28) as long as the input is within the analog input
common mode voltage range.
The resistor, R, in Figure 28 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from V
IN
+ to V
IN
- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source may give better overall system
performance if it is first converted to differential before driving
the HI5766.
Digital Output Control and Clock Requirements
The HI5766 provides a standard high-speed interface to
external TTL logic families.
In order to ensure rated performance of the HI5766, the duty
cycle of the clock should be held at 50%
±
5%. It must also
have low jitter and operate at standard TTL levels.
Performance of the HI5766 will only be guaranteed at
conversion rates above 1 MSPS. This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1 MSPS will have to be
performed before valid data is available.
A Data Format Select (DFS) pin is provided which will
determine the format of the digital data outputs. When at
logic low, the data will be output in offset binary format.
When at logic high, the data will be output in two’s
complement format. Refer to Table 1 for further information.
V
IN
+
V
DC
V
IN
-
HI5766
V
IN
-
V
IN
R
R
C
VDC
VDC
FIGURE 26. DC COUPLED DIFFERENTIAL INPUT
V
IN
+
V
IN
-
HI5766
V
IN
VDC
R
FIGURE 27. AC COUPLED SINGLE ENDED INPUT
V
IN
+
V
IN
-
HI5766
VDC
R
C
V
IN
VDC
FIGURE 28. DC COUPLED SINGLE ENDED INPUT
HI5766
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