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參數(shù)資料
| 型號(hào)： | HI5634 |
| 廠商： | Intersil Corporation |
| 英文描述： | High Performance Programmable Phase-Locked Loop for LCD Applications |
| 中文描述： | 高性能可編程鎖相環(huán)環(huán)路，用于LCD應(yīng)用 |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大?。?/td> | 131K |
| 代理商： | HI5634 |
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11
Register: 6h
Name: Output Enable Register
Access: Read/Write
BIT NAME
BIT #
RESET VALUE
DESCRIPTION
OE_PCK
0
0
Output Enable for CLK Outputs (PECL) - 0 = High Z (default), 1 = Enabled.
OE_TCK
1
0
Output Enable for CLK Output (SSTL_3) - 0 = High Z (default), 1 = Enabled.
OE_P2
2
0
Output Enable for CLK/2 Outputs (PECL) - 0 = High Z (default), 1 = Enabled.
OE_T2
3
0
Output Enable for CLK/2 Output (SSTL_3) - 0 = High Z (default), 1 = Enabled.
OE_F
4
0
Output Enable for FUNC Output (SSTL_3) - 0 = High Z (default), 1 = Enabled.
CK2_INV
5
0
CLK/2 Invert - 0 = Not Inverted (default), 1 = Inverted.
OUT_SCL
6-7
0
Clock (CLK) Scaler.
BIT 7
BIT 6
CLK DIVIDER
0
0
1
0
1
2
1
0
4
1
1
8
Register: 7h
Name: Oscillator Divider Register
Access: Read/Write
BIT NAME
BIT #
RESET VALUE
DESCRIPTION
OSC_DIV0- 6
0-6
0
Oscillator Divider Modulus - Divides the input from OSC (pin 12) by the set modulus.
The modulus equals the programmed value, plus 2. Therefore, the modulus range is from 3 to 129.
IN_SEL
7
1
Input Select - Selects the input to the Phase/Frequency Detector
0 = HSYNC, 1 = Osc Divider (default).
Register: 8h
Name: Reset Register
Access: Write Only
BIT NAME
BIT #
RESET VALUE
DESCRIPTION
DPA Reset
0-3
X
Writing XAh to this register resets DPA working
Register 5.
VALUE
RESETS
XA
DPA
PLL Reset
4-7
X
Writing 5Xh to this register resets PLL working
Registers 1-3.
5X
PLL
5A
DPA and PLL
Register: 10h
Name: Chip Version Register
Access: Read Only
BIT NAME
BIT #
RESET VALUE
DESCRIPTION
CHIP VER
0-7
17
Chip Version 23 (17h).
Register: 11h
Name: Chip Revision Register
Access: Read Only
BIT NAME
BIT #
RESET VALUE
DESCRIPTION
CHIP REV
0-7
01+
Initial value 01h.
+Value increments with each all-layer change.
Register: 12h
Name: Status Register
Access: Read Only
BIT NAME
BIT #
RESET VALUE
DESCRIPTION
DPA_LOCK
0
N/A
DPA Lock Status (Refer to Register 0h, bits 6 and 7). 0 = Unlocked, 1 = Locked.
PLL_LOCK
1
N/A
PLL Lock Status (Refer to Register 0h, bits 6 and 7). 0 = Unlocked, 1 = Locked.
Reserved
2-7
0
Reserved
HI5634
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI5634CB | High Performance Programmable Phase-Locked Loop for LCD Applications |
| HI5640 | 3.3V Dual 8-Bit， 40 MSPS A/D Converter with Internal Voltage Reference (3 pages) FN4657 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5634_00 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Performance Programmable Phase-Locked Loop for LCD Applications |
| HI5634CB | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Performance Programmable Phase-Locked Loop for LCD Applications |
| HI5640 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.3V Dual 8-Bit， 40 MSPS A/D Converter with Internal Voltage Reference (3 pages) FN4657 |
| HI5640CN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| HI-565 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Speed, Monolithic D/A Converter with Reference |
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