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參數(shù)資料
| 型號： | HI-6110PQM |
| 廠商： | HOLT INTEGRATED CIRCUITS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
| 中文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 8/36頁 |
| 文件大小： | 532K |
| 代理商： | HI-6110PQM |
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HOLT INTEGRATED CIRCUITS
8
ISSUINGBCCOMMANDS
Registeroperations intheHI-6110canbeaddressed usingeither
the RA0-RA3 inputs or the RA3:RA0 bits in the Control Register.
Each RA input is logically ORed with its corresponding Control
Register bit. When using input pins for register addressing, the
ControlRegisterbits10:7mustbereset. Registeraddressingvia
Control Register bits 10:7 is a 2-step process. First, the target
register address is written to the Control Register (and the RA0-
RA3inputsmustbeheldlow).Next,thedesiredregisteroperation
is performed: the Control Register provides the register address
whiletheR/
and
inputsspecifydatadirectionandclockthe
datatransfer.
AMIL-STD-1553 Bus Controller message can be pre-loaded into
the HI-6110 by writing the required Command Word to the
Command Word 1 Register. The Command Word 2 register is
used to hold the second (Transmit) Command Word for RT to RT
commands. Message data for MIL-STD-1553 Receive
commands are loaded by the host into the Transmit Data FIFO.
For Mode Code commands with data word, a data word to be
transmittedmustbewrittentotheTransmitDataFIFO.
A BC message sequence commences when a positive edge
occurs at the BCSTART input pin, or when Control Register bit 1
(BCSTART) transitions from 0 to 1 as a result of a register write
operationbytheHost.ControlRegisterbit1isNOTautomatically
reset upon BC message sequence execution. Therefore, when
using the Control Register to start message sequences, it is first
necessarytoresetbit1beforeitissettoinitiatethenextmessage
sequence. TheMIL-STD-1553messageisproperlyformattedby
theHI-6110andoutputontheselectedMIL-STD-1553databus.
The HI-6110 waits for a response from the MIL-STD-1553 bus if
the command type expects a response. The responding RT's
Status Word is captured in the HI-6110 Status Word 1 Register.
The Status Word 2 register is used to capture the Status Word
from the transmitting RT during RT-to-RT transfer commands.
MessagedatawordsreceivedfromthetransmittingRTarestored
in the Receive Data FIFO. A mode data word received from the
transmittingRTisalsostoredintheReceiveDataFIFO.
If the reply from the MIL-STD-1553 responding terminal was a
valid response and met all response time, Sync and Data
encoding,paritychecks,wordcount,RTaddress,andcontiguous
message requirements, then the VALMESS output pin goes high
and bit 7 in the Status Register is set. The host may then retrieve
the contents of the Status Word register(s) and Receive Data
FIFO as required by the application software. The FFEMPTY
output pin will be low if the FIFO contains at least one data word,
and the corresponding bit 3 in the Status Register will be set.
When all data words have been read by the host controller, the
FFEMPTYoutputpingoeshigh,andbit3intheStatusRegisteris
reset.
The final result of any BC message sequence is assertion of
either a VALMESS flag or an ERROR flag. If an error is detected
during a MIL-STD-1553 message sequence, the ERROR output
pin is asserted, corresponding bit 8 in the Status Register is set,
and the appropriate error bit(s) are set in the Error Register. The
host may interrogate the Error Register to determine what action
is necessary to correct the error. The VALMESS output remains
lowforanymessageforwhichanerrorisdetected.
W
STB
HI-6110 (BUS CONTROLLER MODE)
There are limited circumstances when VALMESS may be
followed by ERROR. For example, if the BC requests an RT
response with 4 data words but instead receives 5, the extra data
word will cause the VALMESS flag to be reset and ERROR to be
set. The host controller has the option of reading RT responses
on-the-fly by monitoring the
simplywaitforendofsequenceflags,VALMESSorERROR.
and FFEMPTY flags, or may
While the Transmit Data FIFO may be pre-loaded before starting
a message sequence, any data word may be loaded on the fly, as
long as it is written before mid-sync during that word’s transmit
window. In order to have the full 32 word capacity available, the
Transmit Data FIFO should be cleared before writing data. The
FIFOisclearedatMasterReset,orwhenVALMESSorERRORis
assertedattheendofamessage.
RFLAG
The Receive Data FIFO is cleared at Master Reset, or by
performingaseriesofFIFOreadoperationsuntilFFEMPTYgoes
high. The Receive Data FIFO will not accept new receive data
whenfull.TheFIFOmusthaveatleastoneemptyregisterbymid-
syncwithinthetimewindowforanyincomingdataword.
相關PDF資料 |
PDF描述 |
|---|---|
| HI-6110PQMF | MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
| HI-6110PQT | MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
| HI-6110PQTF | MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
| HI-6110PCI | MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
| HI-6110PCIF | MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HI-6110PQMF | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
| HI-6110PQT | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
| HI-6110PQTF | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
| HI-6120 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:MIL-STD-1553 Remote Terminal ICs |
| HI-6120_10 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:MIL-STD-1553 Remote Terminal ICs |
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