- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384414 > HI-6110PQM (HOLT INTEGRATED CIRCUITS INC) MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor PDF資料下載
參數(shù)資料
| 型號： | HI-6110PQM |
| 廠商： | HOLT INTEGRATED CIRCUITS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
| 中文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 23/36頁 |
| 文件大?。?/td> | 532K |
| 代理商： | HI-6110PQM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
HOLT INTEGRATED CIRCUITS
23
HI-6110 (BUS MONITOR MODE)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MSB
LSB
Bus A/B Word 15:0
BUS
BUS B WORD REGISTER (Read only) Read Address: 1010
(Read only) Read Address: 1001
A WORD REGISTER
MIL-STD-1553 Message Data Word 15:0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MSB
LSB
RECEIVE DATA FIFO (Read only) Read Address: 0100
CONTROL REGISTER (R/W) Write Address: X1XX, Read Address: 1100
RA2
RA1
MRA
RTBCNo Used
MR
MSB
LSB
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
No UNo Used
RA0
REMRB
No UCLReRA3
X
X
X
X
0
REGISTER FORMATS (MT Mode)
The Receive Data FIFO is 32-words deep and holds all MIL-
STD-1553receiveddatawords.TheFIFOisclearedatMaster
Reset.
Alow FFEMPTY flag (output pin or Status register bit) means
FIFOdata is available to be read by the host. Successive data
word fetches will cause FFEMPTY to go high when the last
datawordisread.
TheControlRegistervaluespecifiesHI-6110operatingmode,
clock frequency and specifies which bus is enabled for
monitoring. Control Register bits can also be used for
addressing registers in read/write operations, or to assert
masterreset.
In MT mode, the BusAWord register holds the last valid MIL-
STD-1553 word received on Bus A. The Bus B Word register
holdsthelastvalidMIL-STD-1553wordreceivedonBusB.
BIT
15-13
12
NAME
-
CLKSEL
FUNCTION
NotusedinMTmode.
SelectsthefrequencyoftheHI-6110externalCLKinput,asfollows:
CLKSEL
Value
0
24MHz
1
12MHz
Mustberesetto“0”
10-7
RA3:0
Register Address for HI-6110 register and data read / write operations. The register address is defined by the
logical OR of these bits and their corresponding input pins. Setting Control Register bits 10:7 to 0000 ensures
thatjusttheaddressinputpinscontrolregisteraddressing.
ResetERROR.IfRERRislowtheERRORoutputsignalisonlyresetonreceptionofanewvalid
Setting RERR high
resets a high ERROR output .
(rising edge)
automaticallyresetafter3to4microseconds. Fornormaloperation,thisbitissetto“1”.
protocol engine
both MRA and MRB selects neither bus.
6
RERR
5-4
MRB,MRA Setting either MRA or MRB to "1"connects the
to Monitor BUS A or Monitor BUS B.
The 1553 receiver, Manchester decoder and RCV output signal
remain operational on the inactive bus. When the monitor terminal receives a command on the inactive bus, its
RCV signal output goes high. The MT must switch active buses so received data words, message results, etc.
will be stored in the proper registers. V
alid words received on the inactive bus can be read without changing
activebusbyreadingtheBusAWordorBusBWordRegister,butanyreceivedmessagewords,errors,message
resultsetc.arenotupdatedifthebusisnotenabledbysettingtheappropriateMRAorMRBbit.
3-2
RTMODE, HI-6110 mode select. These Control Register bits are logically OR'ed with their corresponding input pins. The
BCMODE
usercanselect1553operatingmodeundereitherhardwareorsoftwarecontrol:
RTMODE
BCMODE
1553OPERATINGMODE
0
1
BusController(BC)
1
0
RemoteTerminal(RT)
1
1
BusMonitorwithoutassignedRTaddress(MT)
0
0
Bus Monitor with assigned RT address (RT-MT) in which Control Register bits
5:4enabletransmitforvalidcommandsforwhichcommandterminaladdressmatches
theassignedRemoteTerminaladdress. SeetheRTmodesection.
-
NotusedinMTmode.
MR
Master Reset. Writing "1" and then “0” to this bit performs the same function as pulsing the MR pin. All register
and data FIFOs are cleared when master reset is asserted. The Control Register is the exception; it is not
affectedbyMasterReset.
11
Reserved
command.
If the RERR bit is left high, ERROR outputs will
Setting
1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI-6110PQMF | MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
| HI-6110PQT | MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
| HI-6110PQTF | MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
| HI-6110PCI | MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
| HI-6110PCIF | MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI-6110PQMF | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
| HI-6110PQT | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
| HI-6110PQTF | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor |
| HI-6120 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:MIL-STD-1553 Remote Terminal ICs |
| HI-6120_10 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:MIL-STD-1553 Remote Terminal ICs |
發(fā)布緊急采購，3分鐘左右您將得到回復。