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參數(shù)資料
| 型號： | HFA3860IV96 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | 11 Mbps Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48 |
| 文件頁數(shù)： | 34/40頁 |
| 文件大?。?/td> | 250K |
| 代理商： | HFA3860IV96 |
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4-34
Bits 7:0
Test Bus Address = 17h
XOR Fast,
Factory Test Only
Test 7:0 + TEST_CLK = 9 bits of registered XOR test data from the low rate logic.
Bits 7:0
Test Bus Address = 18h
Timing Test,
tests the receiver timing.
Test 7 = JMPCLK
Test 6 = JMPCNT
Test 5 = SUBSAMPLECLK
Test 4:0 = MASTERTIM(4:0)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 19h
A/D Cal Accum Lo,
tests the lo bits of the A/D cal accumulator.
Test 7:0+TestCLK = A/D Cal Accum (8:0)
Bits 7:0
Test Bus Address = 1Ah
A/D Cal Accum Hi,
tests the hi bits of the A/D cal accumulator.
Test 7:0+TestCLK = A/D Cal Accum (17:9)
Bits 7:0
Test Bus Address = 1Bh
Freq Accum Lo,
tests the frequency accumulator of the low rate section.
Test 7:0+TestCLK = Freq Accum (15:7)
Bits 7:0
Test Bus Address = 1Ch
Slow XOR,
Factory Test
Test 7:0 = 8 bits of registered XOR test data from the low rate logic
TEST_CLK = SUBSAMPLECLK
Bits 7:0
Test Bus Address = 1Dh
SQ2 Monitor Hi
Test 7:0 = SQ2 (15:8)
TEST_CLK = pulse after SQ is valid
Bits 7:0
Test Bus Address = 1Eh to 1Fh
Reserved
Test 7:0 + TestCLK = 0
CONFIGURATION REGISTER 28 ADDRESS (70h) TEST BUS ADDRESS (Continued)
Supplies address for test pin outputs and Test Bus Monitor Register
CONFIGURATION REGISTER 29 ADDRESS (74h) TEST BUS MONITOR
Bits 7:0
Maps test bus pins 7:0 to read only value 7:0 when test bus address is supplied by CR 28
CONFIGURATION REGISTER 30 ADDRESS (78h) TEST REGISTER 1
Bits 7
PN Generator for Fault Test
0 = Normal
1 = Enabled
Bit 6
Change MUX Control in Subsample Path
0 = Normal
1 = Changed
Bit 5
HR Demod XOR to Test Bus Enable
0 = Normal
1 = Enabled
Bit 4
Random Address to Test Bus
0 = Normal
1 = Enabled
Bit 3
Faster Cal
0 = Normal
1 = Enabled
When enabled, the 1kHz clock used to update the A/D cal bits is increased to 22kHz.
HFA3860
相關PDF資料 |
PDF描述 |
|---|---|
| HFA3861A | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴頻基帶處理器) |
| HFA3861B | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴譜基帶處理器) |
| HFA3861 | Direct Sequence Spread Spectrum (DSSS) baseband processor(直接序列擴頻基帶處理器) |
| HFA3861IV | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV96 | Direct Sequence Spread Spectrum Baseband Processor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3861 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo |
| HFA3861AIN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo |
| HFA3861AIN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo |
| HFA3861B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
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