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參數(shù)資料
| 型號： | HF88M02 |
| 廠商： | King Billion Electronics Co., Ltd. |
| 英文描述： | 256K x 8 bit Mask ROM |
| 中文描述： | 256K × 8位掩模ROM |
| 文件頁數(shù)： | 8/19頁 |
| 文件大?。?/td> | 322K |
| 代理商： | HF88M02 |
King Billion Electronics Co., Ltd
駿 億 電 子 股 份 有 限 公 司
HF88M02
January 16, 2004
This specification is subject to change without notice. Please contact sales person for the latest version before use.
Page 8 of 19
V1.11
AC1
AC0
P0
DIR0
P1
DIR1
W
W
R/W
R/W
R/W
R/W
Address latch 1 for A15 ~ A8
Address latch 0 for A7 ~ A0
Port 0 Output Register
Direction Register 0
Port 1 Output Register
Direction Register 0
“--------“
“--------“
“11111111“
“00000000“
“11111111“
“00000000“
100
101
110
111
6.1
Retrieve data in Data File
Accesses to the ROM contents, expansion I/O, Address Counter and Direction registers are made through
8 Data I/O pins – D7 ~ D0. With Register Selection RS = “0xx”, the starting addresses can be written
through Data I/Os by bringing WEn to low and back to high. Addresses are latched on the rising edge of
WEn.
Once the starting address of data block is latched into the Address Counter, data may be read out by
sequentially pulsing OEn with CEn staying low. When at ‘0’, the OEn gate the data of the selected
address unto Data I/O pin D7 ~ D0. With the rising edge of OEn, the internal Address Counter is
incremented by one automatically.
6.2
Loading the Address Counter
Before the data can be retrieved, the Address Counter must be initialized with the starting address, then
the contents of ROM pointed to by Address Counter (AC) can be accessed through D7 through D0. In
order to simplify the procedure of loading 19-bit Address Counter (AC), a internal pointer is implemented
and used to point to next register to write in the up to three-cycle address loading sequence. Initially,
with RS = “0xx” CEn goes from ‘1’ to ‘0’ and the AC pointer is initialized. The pointer is then
incremented to point to next register with falling edge of each WEn pulse. So when randomly accessing
data within a 256-byte page, or within a 64K-byte block mode, then only one or two-cycle address reload
process is needed to access different locations within a page or block.
The Address Counter pointer will be held in reset state in the following conditions:
1.
When CEn is '1' (the device is deselected).
2.
By the Read pulse (OEn is '0') and RS2 = '0' (ROM is being accesses).
The inclusion of the 3rd condition is to force the address loading to start from LSB of Address Counter
once the read cycle is initiated. However, the AC Pointer will not be reset when reading or writing
from/to expansion I/O registers (P0, P1, DIR0, DIR1). This design is useful in certain application
scenarios where in the midst of the multi-byte address loading process, an interrupt to the MCU main
loop occurs. And in the interrupt service routine, manipulation of expansion I/O registers is performed,
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