
D. Pin Description
KING BILLION ELECTRONICS CO., LTD
駿
億
電
子
股
份
有
限
公
司
HE8P160E
HE80000 Series
4
Preliminary V1.3E
Pin#
Pin Name
I/O
Function
Description
52, 51
FXI, FXO
B/
O
External fast clock pin.
Connecting to crystal or RC to
generate 32.768 kHz ~ 8MHz
frequency.
55, 54
SXI, SXO
I/
O
External slow clock pin.
Connecting with 32768 Hz crystal
or resistor as slow clock and
providing clock source for LCD
display, TIMER1, Time-Base and
other internal blocks.
Mask option setting
:
MO_FCK/SCKN= 00
:
Slow Clock only
01
:
Illegal
10
:
Dual Clock
11
:
Fast Clock only
MO_FOSCE = 0
:
Internal fast osc.
= 1
:
External fast osc.
MO_FXTAL = 0
:
RC osc. for fast clock
= 1
:
X’tal osc. for fast clock
MO_SXTAL = 0
:
RC for 32768 Hz clock
= 1
:
X’tal for 32768 Hz clock
Use OP1 and OP2 to switch among different operation
mode (NORMAL, SLOW, IDEL and SLEEP). In Dual
Clock mode, the main system clock is still the Fast Clock.
The 32768 Hz clock is for LCD and Timer 1 only.
Level trigger, active low. Except for using this pin, using
mask option (MO_PORE=1) could enable IC build-in
Power-on reset circuit.
Besides, MO_WDTE can set Watch Dog Timer
:
MO_WDTE=0
:
Disable Watch Dog Timer
=1
:
Enable Watch Dog Timer
Please bond this pin and add a test point on PCB for
debugging. But for improving ESD, please connect this
point with zero Ohm resistor to GND.
Mask options
:
MO_CPP[7..0]=1 ~ Push-pull.
= 0 ~ Open-drain.
When use them as input (No tri-state structure), it must
Output “1” before reading.
Mask options
:
MO_DPP[7..0]=1 ~ Push-pull.
= 0 ~ Open-drain.
When use them as input (No tri-state structure), it must
Output “1” before reading.
Mask options
:
MO_LIO14[7..0]=1 ~ LCD Pin.
= 0 ~ I/O Pin.
MO_14PP[7..0]=1 ~ Push-pull.
=0 ~ Open-drain.
When use them as input (No tri-state structure), it must
Output “1” before reading.
Mask options
:
MO_LIO15[7..0]=1 ~ LCD Pin.
=0 ~ I/O Pin.
MO_15PP[7..0]=1 ~ Push-pull.
=0 ~ Open-drain.
Output must be “1” before reading whenever uses them as
input (No tri-state structure).
Please reference LCD and RAM map.
These are LCD segment and OTP Writer shared pin, User
Must refer standard interface to arrange these pins on
PCB board, let KB writer can write data to OTP. These
pins are LCD segment pin on normal mode.
50
RSTP_N
I System Reset.
53
TSTP_P
I
Test Pin, active high.
82, 83
1..6
PRTC[7:0]
/ADC[7:0];
B
Port C bi-directional I/O pin
,
total
8 pin or
ADC[7:0] can be used as
8-channel ADC Data Input Pin.
70..77
PRTD[7:0]
B
8-pin bi-directional I/O port.
PRTD[7..2] as wake-up pin.
PRTD[7..6] as external interrupt
pin.
16..23
PRT14[7:0]/
SEG[23:16]
B/
O
8-pin bi-directional I/O port that is
shared with LCD segment pin.
8..15
PRT15[7:0]/
SEG[31:24]
B/
O
8-pin bi-directional I/O port that is
shared with LCD segment pin.
40..43
COM[3:0]
SEG[15:8]/
D[7:0]
SEG[7]/SDO
SEG[6]/SDI
O LCD COM Output
O LCD segment Output/
OTP writing pin
O Segment/ OTP writing pin
O Segment/ OTP writing pin
24..31
32
33