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參數(shù)資料
| 型號： | HDSP-713G |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | 392 Series Industrial Potentiometer, Conductive Plastic Element, PC Terminals, 0.5 W Power Rating, 2.5 kOhm Resistance Value |
| 中文描述： | 17.3毫米（0.68英寸）通用5x7點陣的字母數(shù)字顯示器 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 458K |
| 代理商： | HDSP-713G |
6
Optical Characteristics at 25
°
C
V
DD
= 5.0 V at Full Brightness
Luminous Intensity
Character Average (#)
Iv (mcd)
Min.
5.0
Peak
Dominant
Wavelength
λ
(nm)
637
Wavelength
λ
(nm)
645
Part
Number
HDSP-2107
-2504
HDSP-2112
-2502
HDSP-2110
-2500
HDSP-2111
-2501
HDSP-2113
-2503
Description
AlGaAs
Typ.
15.0
HER
2.5
7.5
635
626
Orange
2.5
7.5
600
602
Yellow
2.5
7.5
583
585
High
Performance
Green
2.5
7.5
568
574
Note:
1. Refers to the initial case temperature of the device immediately prior to measurement.
[1]
AC Timing Characteristics Over Temperature Range (-45
°
C to +85
°
C)
4.5 V < V
DD
< 5.5 V, unless otherwise specified
Reference
Number
Symbol
1
t
ACC
Display Access Time
Write
Read
2
t
ACS
Address Setup Time to Chip Enable
3
t
CE
Chip Enable Active Time
[2,3]
Write
Read
4
t
ACH
Address Hold Time to Chip Enable
5
t
CER
Chip Enable Recovery Time
6
t
CES
Chip Enable Active Prior to Rising Edge of
[2,3]
Write
Read
7
t
CEH
Chip Enable Hold Time to Rising Edge of
Read/Write Signal
[2,3]
8
t
W
Write Active Time
9
t
WSU
Data Write Setup Time
10
t
WH
Data Write Hold Time
11
t
R
Chip Enable Active Prior to Valid Data
12
t
RD
Read Active Prior to Valid Data
13
t
DF
Read Data Float Delay
t
RC
Reset Active Time
[4]
Description
Min.
[1]
Units
210
230
10
ns
ns
140
160
20
60
ns
ns
ns
140
160
ns
0
ns
ns
ns
ns
ns
ns
ns
ns
100
50
20
160
75
10
300
Notes:
1. Worst case values occur at an IC junction temperature of 150
°
C.
2. For designers who do not need to read from the display, the Read line can be tied to V
DD
and the Write and Chip Enable lines can be
tied together.
3. Changing the logic levels of the Address lines when CE = “0” may cause erroneous data to be entered into the Character RAM,
regardless of the logic levels of the WR and RD lines.
4. The display must not be accessed until after 3 clock pulses (110
μ
s min. using the internal refresh clock) after the rising edge of the
reset line.
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