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參數(shù)資料
| 型號： | HDSP-713G |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | 392 Series Industrial Potentiometer, Conductive Plastic Element, PC Terminals, 0.5 W Power Rating, 2.5 kOhm Resistance Value |
| 中文描述： | 17.3毫米（0.68英寸）通用5x7點陣的字母數(shù)字顯示器 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 458K |
| 代理商： | HDSP-713G |
12
UDC RAM and UDC Address
Register
Figure 3 shows the logic levels
needed to access the UDC RAM
and the UDC Address Register.
The UDC Address Register is
eight bits wide. The lower four
bits (D
0
-D
3
) are used to select one
of the 16 UDC locations. The
upper four bits (D
4
-D
7
) are not
used. Once the UDC address has
been stored in the UDC Address
Register, the UDC RAM can be
accessed.
To completely specify a 5 x 7
character, eight write cycles are
required. One cycle is used to
store the UDC RAM address in the
UDC Address Register and seven
cycles are used to store dot data
in the UDC RAM. Data is entered
by rows and one cycle is needed
to access each row. Figure 4
shows the organization of a UDC
character assuming the symbol to
be stored is an “F.” A
0
-A
2
are used
to select the row to be accessed
and D
0
-D
4
are used to transmit
the row dot data. The upper three
bits (D
5
-D
7
) are ignored. D
0
(least
significant bit) corresponds to the
right most column of the 5 x 7
matrix and D
4
(most significant
bit) corresponds to the left most
column of the 5 x 7 matrix.
Flash RAM
Figure 5 shows the logic levels
needed to access the Flash RAM.
The Flash RAM has one bit
associated with each location of
the Character RAM. The Flash
input is used to select the Flash
RAM while address lines A
3
-A
4
are
ignored. Address lines A
0
-A
2
are
used to select the location in the
Flash RAM to store the attribute.
D
0
is used to store or remove the
flash attribute. D
0
= “1” stores
the attribute and D
0
= “0”
removes the attribute.
When the attribute is enabled
through bit 3 of the Control Word
and a “1” is stored in the Flash
RAM, the corresponding
character will flash at approxi-
mately 2 Hz. The actual rate is
dependent on the clock frequency.
For an external clock the flash
rate can be calculated by dividing
the clock frequency by 28,672.
C
O
L
1
D
4
1
1
1
1
1
1
1
IGNORED
C
O
L
2
D
3
1
0
0
1
0
0
0
C
O
L
3
D
2
1
0
0
1
0
0
0
C
O
L
4
D
1
1
0
0
1
0
0
0
C
O
L
5
D
0
1
0
0
0
0
0
0
HEX
1F
10
10
1D
10
10
10
CH UDC
*
*
*
*
*
*
*
*
*
*
*
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
ROW 6
ROW 7
*
*
*
0 = LOGIC 0; 1 = LOGIC 1; * = ILLUMINATED LED.
Figure 4. Data to Load ""F'' into the UDC RAM.
Figure 3. Logic Levels to Access a UDC Character.
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