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參數(shù)資料
| 型號(hào)： | HDMP-0450 |
| 英文描述： | Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops |
| 中文描述： | 四端口旁路電路的光纖通道仲裁環(huán)路 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 269K |
| 代理商： | HDMP-0450 |
Agilent HDMP-0450
Quad Port Bypass Circuit
for Fibre Channel Arbitrated Loops
Data Sheet
Description
The HDMP-0450 is a Quad Port
Bypass Circuit (PBC) which
provides a low-cost, low-power
physical-layer solution for Fibre
Channel Arbitrated Loop (FC-AL)
disk array configurations. By using a
PBC such as the HDMP-0450, hard
disks may be pulled out or swapped
while other disks in the array are
available to the system.
A PBC consists of multiple 2:1
multiplexers daisy chained together.
Each port has two modes of
operation: “disk in loop” and “disk
bypassed.” When the “disk in loop”
mode is selected, the loop goes into
and out of the disk drive at that
port. For example, data goes from
the HDMP-0450’s TO_NODE[n]
±
differential output pins to the Disk
Drive Transceiver IC’s (e.g., an
HDMP-1636A) Rx differential input
pins. Data from the Disk Drive
Transceiver IC’s Tx differential
outputs goes to the HDMP-0450’s
FM_NODE[n]
±
differential input
Features
Supports 1.0625 GBd Fibre Channel
operation
Supports 1.25 GBd Gigabit Ethernet
(GE) operation
Quad PBC in one package
Signal detect on FM_NODE[0] input
Equalizers on all inputs
High speed LVPECL I/O
Buffered Line Logic (BLL) outputs
(no external bias resistors required)
0.5 W typical power at V
CC
= 3.3 V
44 Pin, 10 mm, low-cost plastic QFP
package
Applications
RAID, JBOD, BTS cabinets
Two 2:1 muxes
Two 1:2 buffers
1 => N gigabit serial buffer
N => 1 gigabit serial mux
CAUTION:
As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling
and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic
discharge (ESD).
pins. Figure 2 shows connection
diagrams for disk drive array
applications. When the “disk
bypassed” mode is selected, the
disk drive is either absent or
nonfunctional and the loop
bypasses the hard disk.
The “disk bypassed” mode is
enabled by pulling the BYPASS[n]-
pin low. Leave BYPASS[n]-
floating to enable the “disk in
loop” mode. HDMP-0450s may be
cascaded with other members of
the HDMP-04XX/HDMP-05XX
family through the appropriate
FM_NODE[n]
±
and
TO_NODE[n]
±
pins to
accommodate any number of hard
disks (see Figure 3). The unused
cells in the HDMP-0450 may be
bypassed by using pulldown
resistors on the BYPASS[n]- pins
for these cells.
An HDMP-0450 may also be
configured as five 1:1 buffers, as
two 2:1 multiplexers, or as two
1:2 buffers.
HDMP-0450
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PDF描述 |
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| HDMP-0452 | Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops |
| HDMP-0552 | AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR AND DATA VALID DETECTION |
| HDMP-1637A | Gigabit Ethernet Serialize/Deserialize (SerDes) with Differential PECL Clock Inputs(帶差分PECL時(shí)鐘輸入的千兆位以太網(wǎng)串行器/解串行器) |
| HDMP-1638 | Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs(帶雙路串行I/O和差分PECL時(shí)鐘輸入的千兆位以太網(wǎng)收發(fā)器) |
| HDMP-2689 | Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-0451 | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0451G | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0452 | 制造商:AGILENT 制造商全稱(chēng):AGILENT 功能描述:Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops |
| HDMP-0480 | 制造商:AGILENT 制造商全稱(chēng):AGILENT 功能描述:Octal Cell Port Bypass Circuit without Clock and Data Recovery |
| HDMP-0482 | 制造商:AGILENT 制造商全稱(chēng):AGILENT 功能描述:Octal Cell Port Bypass Circuit with CDR and Data Valid Detection |
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