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參數(shù)資料
| 型號： | HDMP-0552 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR AND DATA VALID DETECTION |
| 中文描述： | 安捷倫劑量甲基強的松龍與CDR和數(shù)據(jù)有效0552四端口旁路電路檢測 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 266K |
| 代理商： | HDMP-0552 |
Agilent HDMP-0552 Quad Port Bypass
Circuit with CDR and Data Valid
Detection
For Fibre Channel Arbitrated Loops
Data Sheet
Features
Supports 1.0625/2.125 GBd Fibre
Channel operation
Quad PBC/CDR in one package
CDR location determined by
choice of cable input/output
Amplitude valid detection on
FM_NODE[0] input
Data valid detection on
FM_NODE[0] input
–
Run length violation detection
–
Comma detection
– Configurable for both single-
frame and multi-frame
detection
Speed select pin for 1 or 2 GBd
operation
Single REFCLK for 1 or 2 GBd
operation
CDR selectable via external pin
Enable/disable equalizers on all
inputs
Enable/disable selected high-
speed output drivers
High speed LVPECL I/O
Buffered line logic (BLL) outputs
(no external bias resistors
required)
1.1 W typical power at V
CC
= 3.3 V
Advanced 0.35 μ BiCMOS
technology
64 Pin, 10 mm, low cost plastic
QFP package
Applications
RAID, JBOD, BTS cabinets
1=> 1-4 serial buffer with or
without CDR
Description
The HDMP-0552 is a Quad Port
Bypass Circuit (PBC) with Clock
and Data Recovery (CDR) and
data valid detection capability
included. See Figure 1 for block
diagram. This device minimizes
part count, cost and jitter
accumulation while repeating
incoming signals. Port Bypass
Circuits are used in hard disk
arrays constructed in Fibre
Channel Arbitrated Loop (FC-AL)
configurations. By using Port
Bypass Circuits, hard disks may
be pulled out or swapped while
other disks in the array are
available to the system.
A PBC consists of multiple 2:1
multiplexers daisy chained along
with a CDR. Each port has two
modes of operation: “disk in
loop” and “disk bypassed.” When
the “disk in loop” mode is
selected, the loop goes into and
out of the disk drive at that port.
For example, data goes from the
HDMP-0552’s TO_NODE[n]±
differential output pins to the
Disk Drive Transceiver IC (for
example, an HDMP-263x) Rx±
differential input pins. Data from
the Disk Drive Transceiver IC
Tx± differential output pins goes
to HDMP-0552’s FM_NODE[n]±
differential input pins. Figure 2
and Figure 3 show connection
diagrams for disk drive array
applications. When the “disk
bypassed” mode is selected, the
disk drive is either absent or
nonfunctional, and the loop
bypasses the hard disk.
Multiple HDMP-0552’s may be
cascaded or connected to other
members of the HDMP-04xx
family through the FM_LOOP and
TO_LOOP pins to create loops for
arrays of disk drives greater than
4. See Table 3 to identify which
of the 5 cells (0:4) provides
FM_LOOP, TO_LOOP pins (cell
connected to cable).
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assembly of
this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).
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