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參數(shù)資料
| 型號(hào)： | HDMP-1637A |
| 英文描述： | Gigabit Ethernet Serialize/Deserialize (SerDes) with Differential PECL Clock Inputs(帶差分PECL時(shí)鐘輸入的千兆位以太網(wǎng)串行器/解串行器) |
| 中文描述： | 千兆以太網(wǎng)序列化/反序列化器（SerDes）與差分PECL時(shí)鐘輸入（帶差分PECL的時(shí)鐘輸入的千兆位以太網(wǎng)串行器/解串行器） |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大?。?/td> | 249K |
| 代理商： | HDMP-1637A |
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HDMP-1637A SerDes
Gigabit Ethernet SerDes Circuit
with Differential PECL Clock
Inputs
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in handling
and assembly of this component to prevent damage and/or degradation which may be induced by
electrostatic discharge (ESD).
Features
IEEE 802.3z Gigabit
Ethernet Compatible,
Supports 1250 MBd Gigabit
Ethernet
Based on X3T11 “10 Bit
Specification”
Low Power Consumption
10 mm 64-pin PQFP Package
Transmitter and Receiver
Functions Incorporated
onto a Single IC
5-Volt Tolerant I/Os
10 Bit Wide Parallel TTL
Compatible I/Os
Single +3.3 V Power Supply
Differential PECL Clock
Inputs
2 kV Human Body ESD
Protection on all Pins
Applications
1250 MBd Gigabit
Ethernet Interface
High Speed Proprietary
Interface
Backplane Serialization /
Bus Extender
Description
The HDMP-1637A transceiver is a
single silicon bipolar integrated
circuit packaged in a plastic QFP
package. It provides a low-cost,
low-power physical layer solution
for 1250 MBd Gigabit Ethernet or
proprietary link interfaces. It
provides complete Serialize/
Deserialize (SerDes) for copper
transmission, incorporating both
the Gigabit Ethernet transmit and
receive functions into a single
device.
This chip is used to build a high
speed interface (as shown in
Figure 1) while minimizing board
space, power, and cost. It is
compatible with the IEEE 802.3z
specification.
The transmitter section accepts
10-bit wide parallel TTL data and
serializes this data into a high
speed serial data stream. The
parallel data is expected to be
“8B/10B” encoded data, or
equivalent. This parallel data is
latched into the input register of
the transmitter section on the
rising edge of the 125 MHz
reference clock (used as the
transmit byte clock).
The transmitter section’s PLL
locks to this user supplied 125
MHz byte clock. This clock is then
multiplied by 10, to generate the
1250 MHz serial signal clock used
to generate the high speed output.
The high speed outputs are
capable of interfacing directly to
copper cables for electrical
transmission or to a separate fiber
optic module for optical
transmission.
The receiver section accepts a
serial electrical data stream at
1250 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
recovers the high speed serial
clock and data. The serial data is
converted back into 10-bit parallel
data, recognizing the 8B/10B
comma character to establish byte
alignment.
The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two 62.5
MHz receiver byte clocks which
are 180 degrees out of phase with
each other. The parallel data is
properly aligned with the rising
edge of alternating clocks.
For test purposes, the transceiver
provides for on-chip local loop-
back functionality controlled
through an external input pin.
Additionally, the byte
synchronization feature may be
disabled. This may be useful in
proprietary applications which use
alternative methods to align the
parallel data.
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