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參數(shù)資料
| 型號(hào)： | HD74LV573A |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Octal D-type Transparent Latches with 3-state Outputs |
| 中文描述： | 八路D型透明鎖存器與三態(tài)輸出 |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大小： | 66K |
| 代理商： | HD74LV573A |
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HD74LV573A
Octal D-type Transparent Latches with 3-state Outputs
ADE-205-279A (Z)
2nd Edition
July 1999
Description
The HD74LV573A has eight D-type latches with three-state outputs in a 20-pin package. When the latch
enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D
inputs will be retained at the outputs until latch enable returns high again. When a high logic level is
applied to the output control input, all outputs go to a high impedance state, regardless of what signals are
present at the other inputs and the state of the storage elements. Low-voltage and high-speed operation is
suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption
extends the battery life.
Features
V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25
°
C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25
°
C)
Output current
±
8 mA (@V
CC
= 3.0 V to 3.6 V),
±
16 mA (@V
CC
= 4.5 V to 5.5 V)
Function Table
Inputs
OE
LE
D
Output Q
L
H
H
H
L
H
L
L
L
L
X
Q
0
Z
H
Note:
X
X
H:
L:
X:
Z:
Q
0
: Output level before the indicated steady state input conditions were established
High level
Low level
Immaterial
High impedance
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